Information

CMPx_FPR field descriptions
Field Description
7–0
FILT_PER
Filter Sample Period
When CR1[SE] is equal to zero, this field specifies the sampling period, in bus clock cycles, of the
comparator output filter. Setting FILT_PER to 0x0 disables the filter. Filter programming and latency
details appear in the Functional Description.
This field has no effect when CR1[SE] is equal to one. In that case, the external SAMPLE signal is used
to determine the sampling period.
33.7.4 CMP Status and Control Register (CMPx_SCR)
Addresses: CMP0_SCR is 4007_3000h base + 3h offset = 4007_3003h
CMP1_SCR is 4007_3008h base + 3h offset = 4007_300Bh
CMP2_SCR is 4007_3010h base + 3h offset = 4007_3013h
Bit 7 6 5 4 3 2 1 0
Read 0
DMAEN SMELB IER IEF
CFR CFF COUT
Write w1c w1c
Reset
0 0 0 0 0 0 0 0
CMPx_SCR field descriptions
Field Description
7
Reserved
This read-only field is reserved and always has the value zero.
6
DMAEN
DMA Enable Control
The DMAEN bit enables the DMA transfer triggered from the CMP module. When this bit is set, a DMA
request is asserted when the CFR or CFF bit is set.
0 DMA disabled.
1 DMA enabled.
5
SMELB
Stop Mode Edge/Level Interrupt Control
This bit controls whether the CFR and CFF bits are edge sensitive or level sensitive in Stop mode.
NOTE: This bit should always be programmed to 0 to keep the comparator working and to wake up the
MCU.
0 CFR/CFF are level sensitive in Stop mode. CFR will be asserted when COUT is high. CFF will be
asserted when COUT is low.
1 CFR/CFF are edge sensitive in Stop mode. An active low-to-high transition must be seen on COUT to
assert CFR, and an active high-to-low transition must be seen on COUT to assert CFF.
4
IER
Comparator Interrupt Enable Rising
The IER bit enables the CFR interrupt from the CMP. When this bit is set, an interrupt will be asserted
when the CFR bit is set.
Table continues on the next page...
Memory Map/Register Definitions
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
784 Freescale Semiconductor, Inc.