Information

Crossbar Switch
Slave Modules
SDHC
Master Modules
M2
M5
M0
M1
S0
S3
ARM core
code bus
ARM core
system bus
DMA
EzPort
Mux
Flash
controller
S1
SRAM
backdoor
S2
Peripheral
bridge 0
Memory protection unit
(MPU)
Mux
Peripheral
bridge 1
GPIO
controller
S4
FlexBus
MPU
USB
M4
Figure 3-10. Crossbar switch integration
Table 3-15. Reference links to related information
Topic Related module Reference
Full description Crossbar switch Crossbar Switch
System memory map System memory map
Clocking Clock Distribution
Memory protection MPU MPU
Crossbar switch master ARM Cortex-M4 core ARM Cortex-M4 core
Crossbar switch master DMA controller DMA controller
Crossbar switch master EzPort EzPort
Crossbar switch master USB FS/LS USB FS/LS
Crossbar switch master SDHC SDHC
Crossbar switch slave Flash Flash
Crossbar switch slave SRAM backdoor SRAM backdoor
Crossbar switch slave Peripheral bridges Peripheral bridge
Table continues on the next page...
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 81