Information

PDB memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_6000 Status and Control Register (PDB0_SC) 32 R/W 0000_0000h
36.3.1/
831
4003_6004 Modulus Register (PDB0_MOD) 32 R/W 0000_FFFFh
36.3.2/
833
4003_6008 Counter Register (PDB0_CNT) 32 R 0000_0000h
36.3.3/
834
4003_600C Interrupt Delay Register (PDB0_IDLY) 32 R/W 0000_FFFFh
36.3.4/
834
4003_6010 Channel n Control Register 1 (PDB0_CH0C1) 32 R/W 0000_0000h
36.3.5/
835
4003_6014 Channel n Status Register (PDB0_CH0S) 32 w1c 0000_0000h
36.3.6/
836
4003_6018 Channel n Delay 0 Register (PDB0_CH0DLY0) 32 R/W 0000_0000h
36.3.7/
837
4003_601C Channel n Delay 1 Register (PDB0_CH0DLY1) 32 R/W 0000_0000h
36.3.8/
837
4003_6038 Channel n Control Register 1 (PDB0_CH1C1) 32 R/W 0000_0000h
36.3.5/
835
4003_603C Channel n Status Register (PDB0_CH1S) 32 w1c 0000_0000h
36.3.6/
836
4003_6040 Channel n Delay 0 Register (PDB0_CH1DLY0) 32 R/W 0000_0000h
36.3.7/
837
4003_6044 Channel n Delay 1 Register (PDB0_CH1DLY1) 32 R/W 0000_0000h
36.3.8/
837
4003_6150 DAC Interval Trigger n Control Register (PDB0_DACINTC0) 32 R/W 0000_0000h
36.3.9/
838
4003_6154 DAC Interval n Register (PDB0_DACINT0) 32 R/W 0000_0000h
36.3.10/
838
4003_6158 DAC Interval Trigger n Control Register (PDB0_DACINTC1) 32 R/W 0000_0000h
36.3.9/
838
4003_615C DAC Interval n Register (PDB0_DACINT1) 32 R/W 0000_0000h
36.3.10/
838
4003_6190 Pulse-Out n Enable Register (PDB0_PO0EN) 32 R/W 0000_0000h
36.3.11/
839
4003_6194 Pulse-Out n Delay Register (PDB0_PO0DLY) 32 R/W 0000_0000h
36.3.12/
839
Memory Map and Register Definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
830 Freescale Semiconductor, Inc.