Information

36.3.1 Status and Control Register (PDBx_SC)
Addresses: PDB0_SC is 4003_6000h base + 0h offset = 4003_6000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
LDMOD
PDBEIE
0
W
SWTRIG
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DMAEN
PRESCALER TRGSEL
PDBEN
PDBIF
PDBIE
0
MULT
CONT
LDOK
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_SC field descriptions
Field Description
31–20
Reserved
This read-only field is reserved and always has the value zero.
19–18
LDMOD
Load Mode Select
Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers, after 1 is written to
LDOK.
00 The internal registers are loaded with the values from their buffers immediately after 1 is written to
LDOK.
01 The internal registers are loaded with the values from their buffers when the PDB counter reaches
the MOD register value after 1 is written to LDOK.
10 The internal registers are loaded with the values from their buffers when a trigger input event is
detected after 1 is written to LDOK.
11 The internal registers are loaded with the values from their buffers when either the PDB counter
reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.
17
PDBEIE
PDB Sequence Error Interrupt Enable
This bit enables the PDB sequence error interrupt. When this bit is set, any of the PDB channel sequence
error flags generates a PDB sequence error interrupt.
0 PDB sequence error interrupt disabled.
1 PDB sequence error interrupt enabled.
16
SWTRIG
Software Trigger
When PDB is enabled and the software trigger is selected as the trigger input source, writing 1 to this bit
reset and restarts the counter. Writing 0 to this bit has no effect. Reading this bit results 0.
Table continues on the next page...
Chapter 36 Programmable Delay Block (PDB)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 831