Information

3.3.7.2 MPU Logical Bus Master Assignments
The logical bus master assignments for the MPU are:
Table 3-18. MPU Logical Bus Master Assignments
MPU Logical Bus Master Number Bus Master
0 Core
1 Debugger
2 DMA
3 none
4 USB
5 SDHC
6 none
7 none
3.3.7.3 MPU Access Violation Indications
Access violations detected by the MPU are signaled to the appropriate bus master as
shown below:
Table 3-19. Access Violation Indications
Bus Master Core Indication
Core Bus fault (interrupt vector #5) Note: To enable bus faults set the core's System
Handler Control and State Register's BUSFAULTENA bit. If this bit is not set, MPU
violations result in a hard fault (interrupt vector #3).
Debugger The STICKYERROR flag is set in the Debug Port Control/Status Register.
DMA Interrupt vector #32
USB_OTG Interrupt vector #89
SDHC Interrupt vector #96
3.3.7.4 Reset Values for RGD0 Registers
At reset, the MPU is enabled with a single region descriptor (RGD0) that maps the entire
4 GB address space with read, write and execute permissions given to the core, debugger
and the DMA bus masters.
The following table shows the chip-specific reset values for RGD0 and RGDAAC0.
System modules
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
84 Freescale Semiconductor, Inc.