Information

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 80 (12x12) 32-Bit 100 MHz I/O number 52

FTMx_OUTMASK field descriptions

Field Description

31–8

Reserved

This read-only field is reserved and always has the value zero.

7

CH7OM

Channel 7 Output Mask

Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate

normally).

0 Channel output is not masked. It continues to operate normally.

1 Channel output is masked. It is forced to its inactive state.

6

CH6OM

Channel 6 Output Mask

Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate

normally).

0 Channel output is not masked. It continues to operate normally.

1 Channel output is masked. It is forced to its inactive state.

5

CH5OM

Channel 5 Output Mask

Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate

normally).

0 Channel output is not masked. It continues to operate normally.

1 Channel output is masked. It is forced to its inactive state.

4

CH4OM

Channel 4 Output Mask

Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate

normally).

0 Channel output is not masked. It continues to operate normally.

1 Channel output is masked. It is forced to its inactive state.

3

CH3OM

Channel 3 Output Mask

Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate

normally).

0 Channel output is not masked. It continues to operate normally.

1 Channel output is masked. It is forced to its inactive state.

2

CH2OM

Channel 2 Output Mask

Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate

normally).

0 Channel output is not masked. It continues to operate normally.

1 Channel output is masked. It is forced to its inactive state.

1

CH1OM

Channel 1 Output Mask

Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate

normally).

0 Channel output is not masked. It continues to operate normally.

1 Channel output is masked. It is forced to its inactive state.

Table continues on the next page...

Memory Map and Register Definition

K20 Sub-Family Reference Manual, Rev. 6, Nov 2011

876 Freescale Semiconductor, Inc.