Information

FTMx_POL field descriptions (continued)
Field Description
0 The channel polarity is active high.
1 The channel polarity is active low.
0
POL0
Channel 0 Polarity
Defines the polarity of the channel output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The channel polarity is active high.
1 The channel polarity is active low.
37.3.18 Fault Mode Status (FTMx_FMS)
This register contains the fault detection flags, write protection enable bit, and the logic
OR of the enabled fault inputs.
Addresses: FTM0_FMS is 4003_8000h base + 74h offset = 4003_8074h
FTM1_FMS is 4003_9000h base + 74h offset = 4003_9074h
FTM2_FMS is 400B_8000h base + 74h offset = 400B_8074h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FAULTF
WPEN
FAULTIN
0
FAULTF3 FAULTF2 FAULTF1 FAULTF0
W
0
0 0 0 0
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_FMS field descriptions
Field Description
31–8
Reserved
This read-only field is reserved and always has the value zero.
Table continues on the next page...
Chapter 37 FlexTimer (FTM)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 887