Information

Table 3-24. DMA request sources - MUX 0 (continued)
Source
number
Source module Source description
27 FTM0 Channel 3
28 FTM0 Channel 4
29 FTM0 Channel 5
30 FTM0 Channel 6
31 FTM0 Channel 7
32 FTM1 Channel 0
33 FTM1 Channel 1
34 FTM2 Channel 0
35 FTM2 Channel 1
36 FTM3 Channel 0
37 FTM3 Channel 1
38 FTM3 Channel 2
39 FTM1 Channel 3
40 ADC0 —
41 ADC1 —
42 CMP0 —
43 CMP1 —
44 CMP2 —
45 DAC0 —
46 Reserved —
47 CMT —
48 PDB —
49 Port control module Port A
50 Port control module Port B
51 Port control module Port C
52 Port control module Port D
53 Port control module Port E
54 FTM3 Channel 4
55 FTM3 Channel 5
56 FTM3 Channel 6
57 FTM3 Channel 7
58 DMA MUX Always enabled
59 DMA MUX Always enabled
60 DMA MUX Always enabled
Table continues on the next page...
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 89