Information

37.3.22 Configuration (FTMx_CONF)
This register selects the number of times that the FTM counter overflow should occur
before the TOF bit to be set, the FTM behavior in BDM modes, the use of an external
global time base, and the global time base signal generation.
Addresses: FTM0_CONF is 4003_8000h base + 84h offset = 4003_8084h
FTM1_CONF is 4003_9000h base + 84h offset = 4003_9084h
FTM2_CONF is 400B_8000h base + 84h offset = 400B_8084h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
GTBEOUT
GTBEEN
0
BDMMODE
0
NUMTOF
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_CONF field descriptions
Field Description
31–11
Reserved
This read-only field is reserved and always has the value zero.
10
GTBEOUT
Global time base output
Enables the global time base signal generation to other FTMs.
0 A global time base signal generation is disabled.
1
A global time base signal generation is enabled.
9
GTBEEN
Global time base enable
Configures the FTM to use an external global time base signal that is generated by another FTM.
0 Use of an external global time base is disabled.
1
Use of an external global time base is enabled.
8
Reserved
This read-only field is reserved and always has the value zero.
7–6
BDMMODE
BDM Mode
Selects the FTM behavior in BDM mode. See BDM Mode.
5
Reserved
This read-only field is reserved and always has the value zero.
Table continues on the next page...
Chapter 37 FlexTimer (FTM)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 895