Information

37.3.24 Synchronization Configuration (FTMx_SYNCONF)
This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
and CNTIN registers synchronization, if FTM clears the TRIGj bit (where j = 0, 1, 2)
when the hardware trigger j is detected.
Addresses: FTM0_SYNCONF is 4003_8000h base + 8Ch offset = 4003_808Ch
FTM1_SYNCONF is 4003_9000h base + 8Ch offset = 4003_908Ch
FTM2_SYNCONF is 400B_8000h base + 8Ch offset = 400B_808Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
HWSOC
HWINVC
HWOM
HWWRBUF
HWRSTCNT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SWSOC
SWINVC
SWOM
SWWRBUF
SWRSTCNT
SYNCMODE
0
SWOC
INVC
0
CNTINC
0
HWTRIGMODE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_SYNCONF field descriptions
Field Description
31–21
Reserved
This read-only field is reserved and always has the value zero.
20
HWSOC
Software output control synchronization is activated by a hardware trigger.
0 A hardware trigger does not activate the SWOCTRL register synchronization.
1 A hardware trigger activates the SWOCTRL register synchronization.
19
HWINVC
Inverting control synchronization is activated by a hardware trigger.
0 A hardware trigger does not activate the INVCTRL register synchronization.
1 A hardware trigger activates the INVCTRL register synchronization.
18
HWOM
Output mask synchronization is activated by a hardware trigger.
0 A hardware trigger does not activate the OUTMASK register synchronization.
1 A hardware trigger activates the OUTMASK register synchronization.
17
HWWRBUF
MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.
0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
Table continues on the next page...
Memory Map and Register Definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
898 Freescale Semiconductor, Inc.