Information

FTMx_INVCTRL field descriptions (continued)
Field Description
0 Inverting is disabled.
1 Inverting is enabled.
0
INV0EN
Pair Channels 0 Inverting Enable
0 Inverting is disabled.
1 Inverting is enabled.
37.3.26 FTM Software Output Control (FTMx_SWOCTRL)
This register enables software control of channel (n) output and defines the value forced
to the channel (n) output:
• The CHnOC bits enable the control of the corresponding channel (n) output by
software.
• The CHnOCV bits select the value that is forced at the corresponding channel (n)
output.
This register has a write buffer. The fields are updated by the SWOCTRL register
synchronization.
Addresses: FTM0_SWOCTRL is 4003_8000h base + 94h offset = 4003_8094h
FTM1_SWOCTRL is 4003_9000h base + 94h offset = 4003_9094h
FTM2_SWOCTRL is 400B_8000h base + 94h offset = 400B_8094h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CH7OCV CH6OCV CH5OCV CH4OCV CH3OCV CH2OCV CH1OCV CH0OCV
CH7OC CH6OC CH5OC CH4OC CH3OC CH2OC CH1OC CH0OC
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_SWOCTRL field descriptions
Field Description
31–16
Reserved
This read-only field is reserved and always has the value zero.
Table continues on the next page...
Chapter 37 FlexTimer (FTM)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 901