Information

37.4.11.10 FTM Counter Synchronization
The FTM counter synchronization is a mechanism that allows the FTM to re-start the
PWM generation at a certain point in the PWM period. The channels outputs are forced
to their initial value (except for channels in output compare mode) and the FTM counter
is forced to its initial counting value defined by CNTIN register.
The following figure shows the FTM counter synchronization. Note that after the
synchronization event had occurred the channel (n) is set to its initial value and the
channel (n+1) is not set to its initial value due to a specific timing of this figure in which
the deadtime insertion prevents this channel output from transitioning to 1. If no deadtime
insertion is selected then the channel (n+1) transitions to logical value 1 immediately
after the synchronization event had occurred.
synchronization event
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
(after deadtime
insertion)
channel (n+1) output
(after deadtime
insertion)
Figure 37-220. FTM Counter Synchronization
The FTM counter synchronization can be done by either the enhanced PWM
synchronization (SYNCMODE = 1) or the legacy PWM synchronization (SYNCMODE
= 0). However, it is expected that the FTM counter be synchronized only by the enhanced
PWM synchronization.
In the case of enhanced PWM synchronization, the FTM counter synchronization
depends on SWRSTCNT and HWRSTCNT bits according to the following flowchart.
Functional Description
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
942 Freescale Semiconductor, Inc.