Information

The C(n)V register stores the value of FTM counter when the selected edge by channel
(n) is detected at channel (n) input. The C(n+1)V register stores the value of FTM
counter when the selected edge by channel (n+1) is detected at channel (n) input.
In this mode, the pair channels coherency mechanism ensures coherent data when the
C(n)V and C(n+1)V registers are read. The only requirement is that C(n)V must be read
before C(n+1)V.
Note
• The CH(n)F, CH(n)IE, MS(n)A, ELS(n)B, and ELS(n)A
bits are channel (n) bits.
• The CH(n+1)F, CH(n+1)IE, MS(n+1)A, ELS(n+1)B, and
ELS(n+1)A bits are channel (n+1) bits.
• It is expected that the dual edge capture mode be used with
ELS(n)B:ELS(n)A = 0:1 or 1:0, ELS(n+1)B:ELS(n+1)A =
0:1 or 1:0 and the FTM counter in free running counter
mode (Free Running Counter).
37.4.24.1 One-Shot Capture Mode
The one-shot capture mode is selected when (FTMEN = 1), (DECAPEN = 1), and
(MS(n)A = 0). In this capture mode, only one pair of edges at the channel (n) input is
captured. The ELS(n)B:ELS(n)A bits select the first edge to be captured, and ELS(n
+1)B:ELS(n+1)A bits select the second edge to be captured.
The edge captures are enabled while DECAP bit is set. For each new measurement in
one-shot capture mode, first the CH(n)F and CH(n+1) bits must be cleared, and then the
DECAP bit must be set.
In this mode, the DECAP bit is automatically cleared by FTM when the edge selected by
channel (n+1) is captured. Therefore, while DECAP bit is set, the one-shot capture is in
process. When this bit is cleared, both edges were captured and the captured values are
ready for reading in the C(n)V and C(n+1)V registers.
Similarly, when the CH(n+1)F bit is set, both edges were captured and the captured
values are ready for reading in the C(n)V and C(n+1)V registers.
Chapter 37 FlexTimer (FTM)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 963