Information

Device Program flash (KB) Block 0 (P-Flash)
address range
1
Block 1 (P-Flash)
address range
1
MK20DN512ZVLK10 512 0x0000_0000 –
0x0003_FFFF
0x0004_0000 –
0x0007_FFFF
MK20DX256ZVMB10 256 0x0000_0000 –
0x0003_FFFF
0x1000_0000 –
0x1003_FFFF
MK20DN512ZVMB10 512 0x0000_0000 –
0x0003_FFFF
0x0004_0000 –
0x0007_FFFF
1. The addresses shown assume program flash swap is disabled (default configuration).
3.5.1.3 Flash Memory Map
The various flash memories and the flash registers are located at different base addresses
as shown in the following figure. The base address for each is specified in System
memory map.
Program flash
Flash configuration field
Program flash base address
Flash memory base address
Registers
RAM
Programming acceleration
RAM base address
Figure 3-21. Flash memory map
3.5.1.4 Flash Security
How flash security is implemented on this device is described in Chip Security.
3.5.1.5 Flash Modes
The flash memory operates in NVM normal and NVM special modes. The flash memory
enters NVM special mode when the EzPort is enabled (EZP_CS asserted during reset), or
the system is under debug mode. Otherwise, flash memory operates in NVM normal
mode.
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 97