Information

39.2.1 Detailed signal descriptions
Table 39-2. LPTMR interface-detailed signal descriptions
Signal I/O Description
LPTMR_ALTn I Pulse counter input.
The LPTMR can select one of the input pins to be used in pulse counter mode.
State meaning Assertion-If configured for pulse counter mode with active
high input then assertion causes the LPTMR counter
register to increment.
Negation-If configured for pulse counter mode with active
low input then negation cause the LPTMR counter
register to increment.
Timing Assertion or negation may occur at any time; input may
assert asynchronously to the bus clock.
39.3 Memory map and register definition
NOTE
The LPTMR registers are reset only on a POR or LVD event.
See LPTMR power and reset for more details.
LPTMR memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4004_0000 Low Power Timer Control Status Register (LPTMR0_CSR) 32 R/W 0000_0000h
39.3.1/
996
4004_0004 Low Power Timer Prescale Register (LPTMR0_PSR) 32 R/W 0000_0000h
39.3.2/
997
4004_0008 Low Power Timer Compare Register (LPTMR0_CMR) 32 R/W 0000_0000h
39.3.3/
999
4004_000C Low Power Timer Counter Register (LPTMR0_CNR) 32 R 0000_0000h
39.3.4/
999
Chapter 39 Low power timer (LPTMR)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 995