Datasheet

Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Typ.
1
Max. Unit Notes
I
IND
Input leakage current, digital pins
• V
DD
< V
IN
< 5.5 V — 1 50 μA
4, 5
Z
IND
Input impedance examples, digital pins
• V
DD
= 3.6 V
• V
DD
= 3.0 V
• V
DD
= 2.5 V
• V
DD
= 1.7 V
—
—
—
—
—
—
—
—
48
55
57
85
kΩ
kΩ
kΩ
kΩ
4, 7
R
PU
Internal pullup resistors 20 35 50 kΩ 8
R
PD
Internal pulldown resistors 20 35 50 kΩ 9
1. Typical values characterized at 25°C and VDD = 3.6 V unless otherwise noted.
2. Open drain outputs must be pulled to V
DD
.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
4. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
5. Internal pull-up/pull-down resistors disabled.
6. Characterized, not tested in production.
7. Examples calculated using V
IL
relation, V
DD
, and max I
IND
: Z
IND
=V
IL
/I
IND
. This is the impedance needed to pull a high
signal to a level below V
IL
due to leakage when V
IL
< V
IN
< V
DD
. These examples assume signal source low = 0 V.
8. Measured at V
DD
supply voltage = V
DD
min and Vinput = V
SS
9. Measured at V
DD
supply voltage = V
DD
min and Vinput = V
DD
+
–
Digital input
Source
Z
IND
I
IND
5.2.4 Power mode transition operating behaviors
All specifications except t
POR
, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 100 MHz
• Bus clock = 50 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode: FEI
General
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
16 Freescale Semiconductor, Inc.