Datasheet

5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I
2
C signals.
Table 10. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 — Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100 — ns 3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16 — ns 3
External reset pulse width (digital glitch filter disabled) 100 — ns 3
Mode select (EZP_CS) hold time after reset
deassertion
2 — Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ V
DD
≤ 2.7V
• 2.7 ≤ V
DD
≤ 3.6V
• Slew enabled
• 1.71 ≤ V
DD
≤ 2.7V
• 2.7 ≤ V
DD
≤ 3.6V
—
—
—
—
12
6
36
24
ns
ns
ns
ns
4
Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ V
DD
≤ 2.7V
• 2.7 ≤ V
DD
≤ 3.6V
• Slew enabled
• 1.71 ≤ V
DD
≤ 2.7V
• 2.7 ≤ V
DD
≤ 3.6V
—
—
—
—
12
6
36
24
ns
ns
ns
ns
5
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
5.4 Thermal specifications
General
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
22 Freescale Semiconductor, Inc.