Datasheet

Table 15. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
f
dco
DCO output
frequency range
Low range (DRS=00)
640 × f
fll_ref
20 20.97 25 MHz 2, 3
Mid range (DRS=01)
1280 × f
fll_ref
40 41.94 50 MHz
Mid-high range (DRS=10)
1920 × f
fll_ref
60 62.91 75 MHz
High range (DRS=11)
2560 × f
fll_ref
80 83.89 100 MHz
f
dco_t_DMX32
DCO output
frequency
Low range (DRS=00)
732 × f
fll_ref
— 23.99 — MHz 4, 5
Mid range (DRS=01)
1464 × f
fll_ref
— 47.97 — MHz
Mid-high range (DRS=10)
2197 × f
fll_ref
— 71.99 — MHz
High range (DRS=11)
2929 × f
fll_ref
— 95.98 — MHz
J
cyc_fll
FLL period jitter
• f
VCO
= 48 MHz
• f
VCO
= 98 MHz
—
—
180
150
—
—
ps
t
fll_acquire
FLL target frequency acquisition time — — 1 ms 6
PLL
f
vco
VCO operating frequency 48.0 — 100 MHz
I
pll
PLL operating current
• PLL @ 96 MHz (f
osc_hi_1
= 8 MHz, f
pll_ref
=
2 MHz, VDIV multiplier = 48)
— 1060 — µA
7
I
pll
PLL operating current
• PLL @ 48 MHz (f
osc_hi_1
= 8 MHz, f
pll_ref
=
2 MHz, VDIV multiplier = 24)
— 600 — µA
7
f
pll_ref
PLL reference frequency range 2.0 — 4.0 MHz
J
cyc_pll
PLL period jitter (RMS)
• f
vco
= 48 MHz
• f
vco
= 100 MHz
—
—
120
50
—
—
ps
ps
8
J
acc_pll
PLL accumulated jitter over 1µs (RMS)
• f
vco
= 48 MHz
• f
vco
= 100 MHz
—
—
1350
600
—
—
ps
ps
8
D
lock
Lock entry frequency tolerance ± 1.49 — ± 2.98 %
D
unl
Lock exit frequency tolerance ± 4.47 — ± 5.97 %
t
pll_lock
Lock detector detection time — — 150 × 10
-6
+ 1075(1/
f
pll_ref
)
s 9
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 29