Datasheet

6.6.3.2 12-bit DAC operating behaviors
Table 33. 12-bit DAC operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
I
DDA_DACL
P
Supply current — low-power mode — — 150 μA
I
DDA_DACH
P
Supply current — high-speed mode — — 700 μA
t
DACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
— 100 200 μs 1
t
DACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
— 15 30 μs 1
t
CCDACLP
Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
— 0.7 1 μs 1
V
dacoutl
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
— — 100 mV
V
dacouth
DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
V
DACR
−100
— V
DACR
mV
INL Integral non-linearity error — high speed
mode
— — ±8 LSB 2
DNL Differential non-linearity error — V
DACR
> 2
V
— — ±1 LSB 3
DNL Differential non-linearity error — V
DACR
=
VREF_OUT
— — ±1 LSB 4
V
OFFSET
Offset error — ±0.4 ±0.8 %FSR 5
E
G
Gain error — ±0.1 ±0.6 %FSR 5
PSRR Power supply rejection ratio, V
DDA
≥ 2.4 V 60 — 90 dB
T
CO
Temperature coefficient offset voltage — 3.7 — μV/C 6
T
GE
Temperature coefficient gain error — 0.000421 — %FSR/C
Rop Output resistance load = 3 kΩ — — 250 Ω
SR Slew rate -80h→ F7Fh→ 80h
• High power (SP
HP
)
• Low power (SP
LP
)
1.2
0.05
1.7
0.12
—
—
V/μs
CT Channel to channel cross talk — — -80 dB
BW 3dB bandwidth
• High power (SP
HP
)
• Low power (SP
LP
)
550
40
—
—
—
—
kHz
1. Settling within ±1 LSB
2. The INL is measured for 0 + 100 mV to V
DACR
−100 mV
3. The DNL is measured for 0 + 100 mV to V
DACR
−100 mV
4. The DNL is measured for 0 + 100 mV to V
DACR
−100 mV with V
DDA
> 2.4 V
5. Calculated by a best fit curve from V
SS
+ 100 mV to V
DACR
− 100 mV
6. V
DDA
= 3.0 V, reference select set for V
DDA
(DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to
0x800, temperature range is across the full range of the device
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
50 Freescale Semiconductor, Inc.