Datasheet

Table 44. I
2
C timing (continued)
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
Fall time of SDA and SCL signals t
f
— 300 20 +0.1C
b
5
300 ns
Set-up time for STOP condition t
SU
; STO 4 — 0.6 — µs
Bus free time between STOP and
START condition
t
BUF
4.7 — 1.3 — µs
Pulse width of spikes that must be
suppressed by the input filter
t
SP
N/A N/A 0 50 ns
1. The master mode I
2
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10ns and Output Load = 50pf
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I
2
C bus device can be used in a Standard mode I2C bus system, but the requirement t
SU; DAT
≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t
rmax
+ t
SU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I
2
C bus specification) before the SCL line is released.
6. C
b
= total capacitance of the one bus line in pF.


SDA
SCL
t
HD; STA
t
HD; DAT
t
LOW
t
SU; DAT
t
HIGH
t
SU; STA
SR
P
S
S
t
HD; STA
t
SP
t
SU; STO
t
BUF
t
f
t
r
t
f
t
r
Figure 23. Timing definition for fast and standard mode devices on the I
2
C bus
6.8.8 UART switching specifications
See General switching specifications.
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 59