Datasheet

144
LQFP
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
133 A2 PTD6/
LLWU_P15
ADC0_SE7b ADC0_SE7b PTD6/
LLWU_P15
SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0
134 M10 VSS VSS VSS
135 F8 VDD VDD VDD
136 A1 PTD7 PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1
137 C9 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16
138 B9 PTD9 DISABLED PTD9 I2C0_SDA UART5_TX FB_A17
139 B3 PTD10 DISABLED PTD10 UART5_RTS_
b
FB_A18
140 B2 PTD11 DISABLED PTD11 SPI2_PCS0 UART5_CTS_
b
SDHC0_
CLKIN
FB_A19
141 B1 PTD12 DISABLED PTD12 SPI2_SCK SDHC0_D4 FB_A20
142 C3 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21
143 C2 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22
144 C1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23
8.2 K20 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
Pinout
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
70 Freescale Semiconductor, Inc.