Freescale Semiconductor Product Brief Document Number: K30PB Rev. 8, 5/2011 K30 Family Product Brief Supports all K30 devices Contents 1 Kinetis Portfolio Kinetis is the most scalable portfolio of low power, mixedsignal ARM®Cortex™-M4 MCUs in the industry. Phase 1 of the portfolio consists of five MCU families with over 200 pin-, peripheral- and software-compatible devices.
K70 Family 512KB-1MB 196-256pin Kinetis Portfolio Family Program Flash Packages K60 Family 256KB-1MB 100-256pin K50 Family 128-512KB 64-144pin K40 Family 64-512KB 64-144pin K30 Family 64-512KB 64-144pin K20 Family 32KB-1MB 32-144pin K10 Family 32KB-1MB 32-144pin Low power Mixed signal Encryption and Tamper Detect Key Features USB Segment LCD Operational & transimpedance amplifiers Figure 1.
K30 Family Introduction • EEPROM erase/write times an order of magnitude faster than traditional EEPROM • Multi-function external bus interface capable of interfacing to external memories, gate-array logic, or an LCD • Mixed-signal analog: • Fast, high precision 16-bit ADCs, 12-bit DACs, programmable gain amplifiers, high speed comparators and an internal voltage reference.
K30 Block Diagram Kinetis K30 Family ARM ® Cortex™-M4 Core Debug interfaces DSP Interrupt controller System Memories and Memory Interfaces Internal and external watchdogs Program flash Memory protection FlexMemory DMA Serial programming interface RAM Clocks Phaselocked loop Frequencylocked loop External bus Low/high frequency oscillators Internal reference clocks Low-leakage wakeup Communication Interfaces Human-Machine Interface (HMI) Security Analog Timers CRC 16-bit ADC x2 Timers
Features 4 Features 4.1 Common features among the K30 family All devices within the K30 family features the following at a minimum: Table 1. Common features among all K30 devices Operating characteristics • • • • Voltage range 1.71V - 3.6V Flash memory programming down to 1.
Features Table 1.
Features 4.2 FlexMemory Freescale’s new FlexMemory technology provides an extremely versatile and powerful solution for designers seeking onchip EEPROM and/or additional program or data flash memory. As easy and as fast as SRAM, it requires no user or system intervention to complete programming and erase functions when used as high endurance byte-write/byte-erase EEPROM. EEPROM array size can also be configured for improved endurance to suit application requirements.
Features 4.3 Part Numbers and Packaging Q K## A M FFF T PP CC (N) Tape and Reel (T&R) Qualification status Family Speed (MHz) Key attribute Package identifier Memory Temperature range (°C) Flash size Figure 3.
Features Field Description Values CC Maximum CPU frequency (MHz) • • • • • 5 = 50 MHz 7 = 72 MHz 10 = 100 MHz 12 = 120 MHz 15 = 150 MHz N Packaging type • R = Tape and reel • (Blank) = Trays 4.4 K30 family features The following sections list the differences among the various devices available within the K30 family. The sections are split by levels of performance. The features listed below each part number specify the maximum configuration available on that device.
Features MK30DX256VML7(R) MK30DX128VML7(R) MK30DX256VLL7(R) MK30DX128VLL7(R) MK30DX256VMB7(R) MK30DX128VMB7(R) MK30DX64VMB7(R) MK30DX256VLK7(R) MK30DX128VLK7(R) MK30DX64VLK7(R) MK30DX256VEX7(R) MK30DX128VEX7(R) MK30DX64VEX7(R) MK30DX256VLH7(R) MK30DX128VLH7(R) MC Partnumber MK30DX64VLH7(R) Table 3.
Features MK30DX256VML7(R) MK30DX128VML7(R) MK30DX256VLL7(R) MK30DX128VLL7(R) MK30DX256VMB7(R) MK30DX128VMB7(R) MK30DX64VMB7(R) MK30DX256VLK7(R) MK30DX128VLK7(R) MK30DX64VLK7(R) MK30DX256VEX7(R) MK30DX128VEX7(R) MK30DX64VEX7(R) MK30DX256VLH7(R) MK30DX128VLH7(R) MC Partnumber MK30DX64VLH7(R) Table 3.
Features MK30DX256VML7(R) MK30DX128VML7(R) MK30DX256VLL7(R) MK30DX128VLL7(R) MK30DX256VMB7(R) MK30DX128VMB7(R) MK30DX64VMB7(R) MK30DX256VLK7(R) MK30DX128VLK7(R) MK30DX64VLK7(R) MK30DX256VEX7(R) MK30DX128VEX7(R) MK30DX64VEX7(R) MK30DX256VLH7(R) MK30DX128VLH7(R) MC Partnumber MK30DX64VLH7(R) Table 3.
Features MK30DX256VML7(R) MK30DX128VML7(R) MK30DX256VLL7(R) MK30DX128VLL7(R) MK30DX256VMB7(R) MK30DX128VMB7(R) MK30DX64VMB7(R) MK30DX256VLK7(R) MK30DX128VLK7(R) MK30DX64VLK7(R) MK30DX256VEX7(R) MK30DX128VEX7(R) MK30DX64VEX7(R) MK30DX256VLH7(R) MK30DX128VLH7(R) MC Partnumber MK30DX64VLH7(R) Table 3.
Features MC Partnumber MK30DX128ZVLQ10(R) MK30DX128ZVMD10(R) MK30DX256ZVLQ10(R) MK30DX256ZVMD10(R) MK30DN512ZVLK10(R) MK30DN512ZVMB10(R) MK30DN512ZVLL10(R) MK30DN512ZVMC10(R) MK30DN512ZVLQ10(R) MK30DN512ZVMD10(R) Table 4.
Features MC Partnumber MK30DX128ZVLQ10(R) MK30DX128ZVMD10(R) MK30DX256ZVLQ10(R) MK30DX256ZVMD10(R) MK30DN512ZVLK10(R) MK30DN512ZVMB10(R) MK30DN512ZVLL10(R) MK30DN512ZVMC10(R) MK30DN512ZVLQ10(R) MK30DN512ZVMD10(R) Table 4.
Features MK30DN512ZVMB10(R) MK30DN512ZVLL10(R) MK30DN512ZVMC10(R) MK30DN512ZVLQ10(R) MK30DN512ZVMD10(R) 1x8ch 1x8ch 1x8ch 1x8ch 1x8ch 1x8ch 1x8ch 1x8ch 1x8ch Quad decoder/General purpose/PWM 2x2ch 2x2ch 2x2ch 2x2ch 2x2ch 2x2ch 2x2ch 2x2ch 2x2ch 2x2ch FTM External CLK 2 2 2 2 2 2 2 2 2 2 Low Power Timer 1 1 1 1 1 1 1 1 1 1 PIT 1x4ch 1x4ch 1x4ch 1x4ch 1x4ch 1x4ch 1x4ch 1x4ch 1x4ch 1x4ch PDB 1 1 1 1 1 1 1 1 1 1 CMT(Carrier Module Transmitter
Core modules MC Partnumber MK30DX128ZVLQ10(R) MK30DX128ZVMD10(R) MK30DX256ZVLQ10(R) MK30DX256ZVMD10(R) MK30DN512ZVLK10(R) MK30DN512ZVMB10(R) MK30DN512ZVLL10(R) MK30DN512ZVMC10(R) MK30DN512ZVLQ10(R) MK30DN512ZVMD10(R) Table 4.
System modules • • • • • • Close coupling with Cortex-M4 core's Harvard architecture enables low latency interrupt handling Up to 120 interrupt sources Includes a single non-maskable interrupt 16 levels of priority, with each interrupt source dynamically configurable Supports nesting of interrupts when higher priority interrupts are activated Relocatable vector table 4.5.1.
System modules • • • • Programmable Low Voltage Warning (LVW) interrupt capability Buffered bandgap reference voltage output Factory programmed trim for bandgap and LVD 1 kHz Low Power Oscillator (LPO) 4.5.2.2 DMA Channel Multiplexer (DMA MUX) • 16 independently selectable DMA channel routers • 4 periodic trigger sources available • Each channel router can be assigned to 1 of 64 possible peripheral DMA sources 4.5.2.
Memories and Memory Interfaces • Modulo VCO frequency divider Phase/Frequency detector • Integrated loop filter • Internal reference clock generator • Slow clock with nine trim bits for accuracy • Fast clock with four trim bits • Can be used to control the FLL • Either the slow or the fast clock can be selected as the clock source for the MCU • Can be used as a clock source for other on-chip peripherals • External clock from the Crystal Oscillator (XOSC) • Can be used to control the FLL and/or the PLL • Ca
Security and Integrity 4.5.4 Security and Integrity 4.5.4.1 • • • • • • • Cyclic Redundancy Check (CRC) Hardware CRC generator circuit using 16/32-bit shift register User Configurable 16/32 bit CRC Programmable Generator Polynomial Error detection for all single, double, odd, and most multi-bit errors Programmable initial seed value High-speed CRC calculation Optional feature to transpose input data and CRC result via transpose register, required on applications where bytes are in lsb format 4.5.
Timers • Shorter propagation delay at the expense of higher power • Low power, with longer propagation delay • Operational in all MCU power modes 4.5.5.
Timers • • • • One interval trigger output per DAC One 16-bit delay interval register per DAC trigger output Optional bypass the delay interval trigger registers Optional external triggers • Up to eight pulse outputs (pulse-out's) • Pulse-out's can be enabled or disabled independently. • Programmable pulse width 4.5.6.
Communication interfaces 4.5.6.5 Carrier Modulator Timer (CMT) • Four modes of operation • Time with independent control of high and low times • Baseband • Frequency shift key (FSK) • Direct software control of CMT_IRO signal • • • • Extended space operation in time, baseband, and FSK modes Selectable input clock divider Interrupt on end of cycle Ability to disable CMT_IRO signal and use as timer interrupt 4.5.6.
Communication interfaces • • • • • • • • Slave select output Mode fault error flag with CPU interrupt capability Control of SPI operation during wait mode Selectable MSB-first or LSB-first shifting Programmable 8-bit or 16-bit data transmission length Receive data buffer hardware match feature 64-bit FIFO mode for high speed transfers of large amounts of data Support for both transmit and receive by DMA 4.5.7.
Human-machine interface • SD Memory Card Specification, Version 2.0 (http://www.sdcard.org ), supporting high capacity SD memory cards • SDIO Card Specification, Version 2.0 (http://www.sdcard.org ) • CE-ATA Card Specification, Version 1.0 (http://www.sdcard.
Power modes • Configurable button- and slider-sensitive interrupts • Operation in low-power modes allows wakeup from lowest power mode via a single touch • Option to use internal reference clock 4.5.8.
Power modes The three primary modes of operation are run, wait and stop. The WFI instruction invokes both wait and stop modes for the chip. The primary modes are augmented in a number of ways to provide lower power based on application needs. Table 5. Chip power modes Chip mode Description Normal run Allows maximum performance of chip. Default mode out of reset; onchip voltage regulator is on. Normal Wait via WFI Allows peripherals to function while the core is in sleep mode, reducing power.
Developer Environment Table 5. Chip power modes (continued) Chip mode VLLS1 (Very Low Leakage Stop1) Description Core mode Normal recovery method Most peripherals are disabled (with clocks stopped), but LLWU, LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU is used to wake up. Sleep Deep Wakeup Reset2 Off Power-up Sequence All of SRAM_U and SRAM_L are powered off. The 32-byte system register file and the 32-byte VBAT register file remain powered for customer-critical data.
Developer Environment The Freescale Tower System Primary Elevator MCU/ MPU Module • Common serial and expansion bus signals • Tower controller board • Works stand-alone or in Tower System • Two 2x80 connectors on backside for easy signal access and side-mounting board (i.e.
Developer Environment 6.2 CodeWarrior Development Studio Freescale's CodeWarrior Development Studio for Microcontrollers v10.x integrates the development tools for the RS08, HCS08, ARM, and ColdFire architectures into a single product based on the Eclipse open development platform. Eclipse offers an excellent framework for building software development environments and is becoming a standard framework used by many embedded software vendors. • Eclipse IDE 3.
Developer Environment 6.3 Freescale's MQX™ Software Solutions The increasing complexity of industrial applications and expanding functionality of semiconductors are driving embedded developers toward solutions that combine proven hardware and software platforms. These solutions help accelerate time to market and improve application development success.
Developer Environment • Component-based architecture: Provides a fully-functional RTOS core with additional, optional services. Freescale's MQX RTOS includes 25 components (8 core components and 17 optional). Components are linked in only if needed, preventing unused functions from bloating the memory footprint. • Full and lightweight components: Key components are included in both full and lightweight versions for further control of size, RAM/ROM utilization, and performance options.
Revision History • • • • • • Touch Sensing Software Suite Complimentary Bootloaders (USB, Ethernet, RF, serial) Complimentary Freescale Embedded GUI Complimentary Freescale MQX™ RTOS , USB, TCP/IP stack and MFS filesystem Low Cost Nano™ SSL/Nano™ SSH for Freescale MQX™ RTOS Plus full ARM® ecosystem 7 Revision History The following table provides a revision history for this document. Table 8. Revision History Rev. No.
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