Datasheet

Table 4. K30 100MHz Performance Table (continued)
MC Partnumber
MK30DX128ZVLQ10(R)
MK30DX128ZVMD10(R)
MK30DX256ZVLQ10(R)
MK30DX256ZVMD10(R)
MK30DN512ZVLK10(R)
MK30DN512ZVMB10(R)
MK30DN512ZVLL10(R)
MK30DN512ZVMC10(R)
MK30DN512ZVLQ10(R)
MK30DN512ZVMD10(R)
Graphic LCD - - - - - - - - - -
TSI(Capacitive Touch) 16
input
16
input
16
input
16
input
16
input
16
input
16
input
16
input
16
input
16
input
GPIO (w interrupt) 102 102 102 102 56 56 68 90 102 102
Operating Characteristics
5V Tolerant YES YES YES YES YES YES YES YES YES YES
Voltage Range 1.71-3.
6V
1.71-3.
6V
1.71-3.
6V
1.71-3.
6V
1.71-3.
6V
1.71-3.
6V
1.71-3.
6V
1.71-3.
6V
1.71-3.
6V
1.71-3.
6V
Flash Write V 1.71V 1.71V 1.71V 1.71V 1.71V 1.71V 1.71V 1.71V 1.71V 1.71V
Temp Range -40 to
105C
-40 to
105C
-40 to
105C
-40 to
105C
-40 to
105C
-40 to
105C
-40 to
105C
-40 to
105C
-40 to
105C
-40 to
105C
4.5 Module-by-module feature list
The following sections describe the high-level module features for the family's superset device. See the previous section for
differences among the subset devices.
Core modules
4.5.1.1 ARM Cortex-M4 Core
• Supports up to 100 MHz frequency with 1.25DMIPS/MHz
•
ARM Core based on the ARMv7 Architecture & Thumb
®
-2 ISA
•
Microcontroller cores focused on very cost sensitive, deterministic, interrupt driven environments
• Harvard bus architecture
• 3-stage pipeline with branch speculation
• Integrated bus matrix
• Integrated Digital Signal Processor (DSP)
• Configurable nested vectored interrupt controller (NVIC)
• Advanced configurable debug and trace components
• Embedded Trace Macrocell (ETM)
4.5.1.2 Nested Vectored Interrupt Controller (NVIC)
4.5.1
Core modules
K30 Family Product Brief, Rev. 8, 5/2011
Freescale Semiconductor, Inc. 17