Datasheet

• Close coupling with Cortex-M4 core's Harvard architecture enables low latency interrupt handling
• Up to 120 interrupt sources
• Includes a single non-maskable interrupt
• 16 levels of priority, with each interrupt source dynamically configurable
• Supports nesting of interrupts when higher priority interrupts are activated
• Relocatable vector table
4.5.1.3 Wake-up Interrupt Controller (WIC)
• Supports interrupt handling when system clocking is disabled in low power modes
• Takes over and emulates the NVIC behavior when correctly primed by the NVIC on entry to very-deep-sleep
• A rudimentary interrupt masking system with no prioritization logic signals for wake-up as soon as a non-masked
interrupt is detected
• Contains no programmer’s model visible state and is therefore invisible to end users of the device other than through
the benefits of reduced power consumption while sleeping
4.5.1.4 Debug Controller
• Serial Wire JTAG Debug Port (SWJ-DP) combines
• external interface that provides a standard JTAG or cJTAG interface for debug access
• external interface that provides a serial-wire bidirectional debug interface
• Debug Watchpoint and Trace (DWT) with the following functionality:
• four comparators configurable as a hardware watchpoint, an ETM trigger, a PC sampler event trigger, or a data
address sampler event trigger
• several counters or a data match event trigger for performance profiling
• configurable to emit PC samples at defined intervals or to emit interrupt event information
• Instrumentation Trace Macrocell (ITM) with the following functionality:
• Software trace - writes directly to ITM stimulus registers can cause packets to be emitted
• Hardware trace - packets generated by DWT are emitted by ITM
• Time stamping - emitted relative to packets
• Embedded Trace Macrocell (ETM) supports instruction trace
•
CoreSight
™
Embedded Trace Buffer (ETB) is a memory-mapped buffer to store trace data. Allows reconstruction of
program flow with standard JTAG tools.
• Test Port Interface Unit (TPIU) acts as a bridge between ITM or ETM and an off-chip Trace Port Analyzer
• Flash Patch and Breakpoints (FPB) implements hardware breakpoints and patches code and data from code space to
system space
System modules
4.5.2.1 Power Management Control Unit (PMC)
• Separate digital (regulated) and analog (referenced to digital) supply outputs
•
Programmable power saving modes
• No output supply decoupling capacitors required
• Available wake-up from power saving modes via RTC and external inputs
• Integrated Power-on Reset (POR)
• Integrated Low Voltage Detect (LVD) with reset (brownout) capability
• Selectable LVD trip points
4.5.2
System modules
K30 Family Product Brief, Rev. 8, 5/2011
18 Freescale Semiconductor, Inc.