Datasheet

Security and Integrity
4.5.4.1 Cyclic Redundancy Check (CRC)
Hardware CRC generator circuit using 16/32-bit shift register
User Configurable 16/32 bit CRC
Programmable Generator Polynomial
Error detection for all single, double, odd, and most multi-bit errors
Programmable initial seed value
High-speed CRC calculation
Optional feature to transpose input data and CRC result via transpose register, required on applications where bytes are
in lsb format
Analog
4.5.5.1 16-bit Analog-to-Digital Converter (ADC)
Linear successive approximation algorithm with up to 16-bit resolution
Output modes:
Differential 16-bit, 13-bit, 11-bit, and 9-bit modes, in two’s complement 16-bit sign-extended format
Single-ended 16-bit, 12-bit, 10-bit, and 8-bit modes, in right-justified unsigned format
Single or continuous conversion
Configurable sample time and conversion speed/power
Conversion complete and hardware average complete flag and interrupt
Input clock selectable from up to four sources
Operation in low power modes for lower noise operation
Asynchronous clock source for lower noise operation with option to output the clock
Selectable asynchronous hardware conversion trigger with hardware channel select
Automatic compare with interrupt for various programmable values
Temperature sensor
Hardware average function
Selectable voltage reference
Self-calibration mode
4.5.5.2 High-Speed Analog Comparator (CMP)
6-bit DAC programmable reference generator output
Up to eight selectable comparator inputs; each input can be compared with any input by any polarity sequence
Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output
Comparator output supports:
Sampled
Windowed (ideal for certain PWM zero-crossing-detection applications
Digitally filtered using external sample signal or scaled peripheral clock
Two performance modes:
4.5.4
4.5.5
Security and Integrity
K30 Family Product Brief, Rev. 8, 5/2011
Freescale Semiconductor, Inc. 21