Datasheet

• Shorter propagation delay at the expense of higher power
• Low power, with longer propagation delay
• Operational in all MCU power modes
4.5.5.3 12-Bit Digital-to-Analog Converter (DAC)
• 12-bit resolution
• Guaranteed 6-sigma monotocity over input word
• High- and low-speed conversions
• 1 μs conversion rate for high speed, 2 μs for low speed
• Power-down mode
• Choice of asynchronous or synchronous updates
• Automatic mode allows the DAC to generate its own output waveforms including square, triangle, and sawtooth
• Automatic mode allows programmable period, update rate, and range
• DMA support with configurable watermark level
4.5.5.4 Voltage Reference (VREF)
• Programmable trim register with 0.5mV steps, automatically loaded with room temp value upon reset
• Programmable mode selection:
• Off
• Bandgap out (or stabilization delay)
• Low-power buffer mode
• Tight-regulation buffer mode
• 1.2V output at room temperature
• Dedicated output pin
Timers
4.5.6.1 Programmable Delay Block (PDB)
• Up to 15 trigger input sources and software trigger source
•
Up to eight configurable PDB channels for ADC hardware trigger
• One PDB channel is associated with one ADC.
• One trigger output for ADC hardware trigger and up to eight pre-trigger outputs for ADC trigger select per PDB
channel
• Trigger outputs can be enabled or disabled independently.
• One 16-bit delay register per pre-trigger output
• Optional bypass of the delay registers of the pre-trigger outputs
• Operation in One-Shot or Continuous modes
• Optional back-to-back mode operation, which enables the ADC conversions complete to trigger the next PDB
channel
• One programmable delay interrupt
• One sequence error interrupt
• One channel flag and one sequence error flag per pre-trigger
• DMA support
• Up to eight DAC interval triggers
4.5.6
Timers
K30 Family Product Brief, Rev. 8, 5/2011
22 Freescale Semiconductor, Inc.