Datasheet
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8-bit or 16-bit data transmission length
• Receive data buffer hardware match feature
• 64-bit FIFO mode for high speed transfers of large amounts of data
• Support for both transmit and receive by DMA
4.5.7.3
Inter-Integrated Circuit (I
2
C)
•
Compatible with I
2
C bus standard and SMBus Specification Version 2 features
•
Up to 100 kbps with maximum bus loading
• Multi-master operation
• Software programmable for one of 64 different serial clock frequencies
• Programmable slave address and glitch input filter
• Interrupt or DMA driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Bus busy detection broadcast and 10-bit address extension
• Address matching causes wake-up when processor is in low power mode
4.5.7.4 UART
• Support for ISO 7816 protocol for interfacing with smartcards
•
Full-duplex operation
• Standard mark/space non-return-to-zero (NRZ) format
• 13-bit baud rate selection with fractional divide of 32
• Programmable 8-bit or 9-bit data format
• Separately enabled transmitter and receiver
• Programmable transmitter output polarity
• Programmable receive input polarity
• 13-bit break character option
• 11-bit break character detection option
• Parameterizable buffer support for one dataword for each transmit and receive
• Independent FIFO structure for transmit and receive
• Two receiver wakeup methods:
• Idle line wakeup
• Address mark wakeup
• Address match feature in receiver to reduce address mark wakeup ISR overhead
• Interrupt or DMA driven operation
• Receiver framing error detection
• Hardware parity generation and checking
• 1/16 bit-time noise detection
4.5.7.5 Secure Digital Host Controller (SDHC)
• Compatible with the following specifications:
• SD Host Controller Standard Specification, Version 2.0 (http://www.sdcard.org ) with test event register and
advanced DMA support
• MultiMediaCard System Specification, Version 4.2 (http://www.mmca.org )
Communication interfaces
K30 Family Product Brief, Rev. 8, 5/2011
Freescale Semiconductor, Inc. 25