Datasheet

Table 5. Chip power modes (continued)
Chip mode Description Core mode Normal
recovery
method
VLLS1 (Very
Low Leakage
Stop1)
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU
is used to wake up.
All of SRAM_U and SRAM_L are powered off. The 32-byte system
register file and the 32-byte VBAT register file remain powered for
customer-critical data.
Sleep Deep
Wakeup Reset
2
BAT (backup
battery only)
The chip is powered down except for the VBAT supply. The RTC and
the 32-byte VBAT register file for customer-critical data remain
powered.
Off Power-up
Sequence
1. Resumes normal run mode operation by executing the LLWU interrupt service routine.
2. Follows the reset flow with the LLWU interrupt flag set for the NVIC.
6 Developer Environment
Freescale's products are supported by a widespread, established network of tools and third party developers and software
vendors. The Kinetis families take advantage of these and similar development resources.
6.1 Freescale's Tower System Support
Freescale's Tower System is a modular development platform for 8-bit, 16-bit, and 32-bit microcontrollers that enables
advanced development through rapid prototyping. Featuring multiple development boards or modules, the Tower System
provides designers with building blocks for entry-level to advanced microcontroller development.
Developer Environment
K30 Family Product Brief, Rev. 8, 5/2011
Freescale Semiconductor, Inc. 29