Datasheet

144
LQFP
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
50 J5 PTA0 JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1 PTA0 UART0_CTS_
b
FTM0_CH5 JTAG_TCLK/
SWD_CLK
EZP_CLK
51 J6 PTA1 JTAG_TDI/
EZP_DI
TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI
52 K6 PTA2 JTAG_TDO/
TRACE_SWO/
EZP_DO
TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/
TRACE_SWO
EZP_DO
53 K7 PTA3 JTAG_TMS/
SWD_DIO
TSI0_CH4 PTA3 UART0_RTS_
b
FTM0_CH0 JTAG_TMS/
SWD_DIO
54 L7 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5 PTA4/
LLWU_P3
FTM0_CH1 NMI_b EZP_CS_b
55 M8 PTA5 DISABLED PTA5 FTM0_CH2 CMP2_OUT I2S0_RX_
BCLK
JTAG_TRST
56 E7 VDD VDD VDD
57 G7 VSS VSS VSS
58 J7 PTA6 DISABLED PTA6 FTM0_CH3 FB_CLKOUT TRACE_
CLKOUT
59 J8 PTA7 ADC0_SE10 ADC0_SE10 PTA7 FTM0_CH4 FB_AD18 TRACE_D3
60 K8 PTA8 ADC0_SE11 ADC0_SE11 PTA8 FTM1_CH0 FB_AD17 FTM1_QD_
PHA
TRACE_D2
61 L8 PTA9 DISABLED PTA9 FTM1_CH1 FB_AD16 FTM1_QD_
PHB
TRACE_D1
62 M9 PTA10 DISABLED PTA10 FTM2_CH0 FB_AD15 FTM2_QD_
PHA
TRACE_D0
63 L9 PTA11 DISABLED PTA11 FTM2_CH1 FB_OE_b FTM2_QD_
PHB
64 K9 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 FB_CS5_b/
FB_TSIZ1/
FB_BE23_16_
b
I2S0_TXD FTM1_QD_
PHA
65 J9 PTA13/
LLWU_P4
CMP2_IN1 CMP2_IN1 PTA13/
LLWU_P4
CAN0_RX FTM1_CH1 FB_CS4_b/
FB_TSIZ0/
FB_BE31_24_
b
I2S0_TX_FS FTM1_QD_
PHB
66 L10 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX FB_AD31 I2S0_TX_
BCLK
67 L11 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX FB_AD30 I2S0_RXD
68 K10 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CTS_
b
FB_AD29 I2S0_RX_FS
69 K11 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_
b
FB_AD28 I2S0_MCLK I2S0_CLKIN
70 E8 VDD VDD VDD
71 G8 VSS VSS VSS
72 M12 PTA18 EXTAL EXTAL PTA18 FTM0_FLT2 FTM_CLKIN0
73 M11 PTA19 XTAL XTAL PTA19 FTM1_FLT0 FTM_CLKIN1 LPT0_ALT1
74 L12 RESET_b RESET_b RESET_b
Pinout
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
70 Freescale Semiconductor, Inc.