Datasheet

144
LQFP
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
125 A6 PTC16 LCD_P36 LCD_P36 PTC16 CAN1_RX UART3_RX LCD_P36
126 D5 PTC17 LCD_P37 LCD_P37 PTC17 CAN1_TX UART3_TX LCD_P37
127 C5 PTC18 LCD_P38 LCD_P38 PTC18 UART3_RTS_
b
LCD_P38
128 B5 PTC19 LCD_P39 LCD_P39 PTC19 UART3_CTS_
b
LCD_P39
129 A5 PTD0/
LLWU_P12
LCD_P40 LCD_P40 PTD0/
LLWU_P12
SPI0_PCS0 UART2_RTS_
b
LCD_P40
130 D4 PTD1 LCD_P41/
ADC0_SE5b
LCD_P41/
ADC0_SE5b
PTD1 SPI0_SCK UART2_CTS_
b
LCD_P41
131 C4 PTD2/
LLWU_P13
LCD_P42 LCD_P42 PTD2/
LLWU_P13
SPI0_SOUT UART2_RX LCD_P42
132 B4 PTD3 LCD_P43 LCD_P43 PTD3 SPI0_SIN UART2_TX LCD_P43
133 A4 PTD4/
LLWU_P14
LCD_P44 LCD_P44 PTD4/
LLWU_P14
SPI0_PCS1 UART0_RTS_
b
FTM0_CH4 EWM_IN LCD_P44
134 A3 PTD5 LCD_P45/
ADC0_SE6b
LCD_P45/
ADC0_SE6b
PTD5 SPI0_PCS2 UART0_CTS_
b
FTM0_CH5 EWM_OUT_b LCD_P45
135 A2 PTD6/
LLWU_P15
LCD_P46/
ADC0_SE7b
LCD_P46/
ADC0_SE7b
PTD6/
LLWU_P15
SPI0_PCS3 UART0_RX FTM0_CH6 FTM0_FLT0 LCD_P46
136 M10 VSS VSS VSS
137 F8 VDD VDD VDD
138 A1 PTD7 LCD_P47 LCD_P47 PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1 LCD_P47
139 B3 PTD10 DISABLED PTD10 UART5_RTS_
b
FB_AD9
140 B2 PTD11 DISABLED PTD11 SPI2_PCS0 UART5_CTS_
b
SDHC0_
CLKIN
FB_AD8
141 B1 PTD12 DISABLED PTD12 SPI2_SCK SDHC0_D4 FB_AD7
142 C3 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_AD6
143 C2 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_AD5
144 C1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_RW_b
8.2 K40 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
Pinout
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 73