Datasheet

121
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
J6 PTA0 JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1 PTA0 UART0_CTS_b FTM0_CH5 JTAG_TCLK/
SWD_CLK
EZP_CLK
H8 PTA1 JTAG_TDI/
EZP_DI
TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI
J7 PTA2 JTAG_TDO/
TRACE_SWO/
EZP_DO
TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/
TRACE_SWO
EZP_DO
H9 PTA3 JTAG_TMS/
SWD_DIO
TSI0_CH4 PTA3 UART0_RTS_b FTM0_CH0 JTAG_TMS/
SWD_DIO
J8 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5 PTA4/
LLWU_P3
FTM0_CH1 NMI_b EZP_CS_b
K7 PTA5 DISABLED PTA5 FTM0_CH2 RMII0_RXER/
MII0_RXER
CMP2_OUT I2S0_RX_BCLK JTAG_TRST
E5 VDD VDD VDD
G3 VSS VSS VSS
J9 PTA10 DISABLED PTA10 FTM2_CH0 MII0_RXD2 FTM2_QD_
PHA
TRACE_D0
J4 PTA11 DISABLED PTA11 FTM2_CH1 MII0_RXCLK FTM2_QD_
PHB
K8 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 RMII0_RXD1/
MII0_RXD1
I2S0_TXD FTM1_QD_
PHA
L8 PTA13/
LLWU_P4
CMP2_IN1 CMP2_IN1 PTA13/
LLWU_P4
CAN0_RX FTM1_CH1 RMII0_RXD0/
MII0_RXD0
I2S0_TX_FS FTM1_QD_
PHB
K9 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX RMII0_CRS_
DV/
MII0_RXDV
I2S0_TX_BCLK
L9 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX RMII0_TXEN/
MII0_TXEN
I2S0_RXD
J10 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CTS_b RMII0_TXD0/
MII0_TXD0
I2S0_RX_FS
H10 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_b RMII0_TXD1/
MII0_TXD1
I2S0_MCLK I2S0_CLKIN
L10 VDD VDD VDD
K10 VSS VSS VSS
L11 PTA18 EXTAL EXTAL PTA18 FTM0_FLT2 FTM_CLKIN0
K11 PTA19 XTAL XTAL PTA19 FTM1_FLT0 FTM_CLKIN1 LPT0_ALT1
J11 RESET_b RESET_b RESET_b
H11 PTA29 DISABLED PTA29 MII0_COL FB_A24
G11 PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL FTM1_CH0 RMII0_MDIO/
MII0_MDIO
FTM1_QD_
PHA
G10 PTB1 ADC0_SE9/
ADC1_SE9/
TSI0_CH6
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
PTB1 I2C0_SDA FTM1_CH1 RMII0_MDC/
MII0_MDC
FTM1_QD_
PHB
G9 PTB2 ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
PTB2 I2C0_SCL UART0_RTS_b ENET0_1588_
TMR0
FTM0_FLT3
Pinout
K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
70 Freescale Semiconductor, Inc.