Datasheet

Table 44. Master mode DSPI timing (full voltage range) (continued)
Num Description Min. Max. Unit Notes
DS2 DSPI_SCK output high/low time (t
SCK
/2) - 4 (t
SCK/2)
+ 4 ns
DS3 DSPI_PCSn valid to DSPI_SCK delay (t
BUS
x 2) −
4
— ns 2
DS4 DSPI_SCK to DSPI_PCSn invalid delay (t
BUS
x 2) −
4
— ns 3
DS5 DSPI_SCK to DSPI_SOUT valid — 10 ns
DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 — ns
DS7 DSPI_SIN to DSPI_SCK input setup 20.5 — ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DS3 DS4
DS1
DS2
DS7
DS8
First data
Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 24. DSPI classic SPI timing — master mode
Table 45. Slave mode DSPI timing (full voltage range)
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
Frequency of operation — 6.25 MHz
DS9 DSPI_SCK input cycle time 8 x t
BUS
— ns
DS10 DSPI_SCK input high/low time (t
SCK
/2) - 4 (t
SCK/2)
+ 4 ns
DS11 DSPI_SCK to DSPI_SOUT valid — 20 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns
DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns
DS15 DSPI_SS active to DSPI_SOUT driven — 19 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven — 19 ns
Peripheral operating requirements and behaviors
K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 61