Datasheet

First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 25. DSPI classic SPI timing — slave mode
6.8.8 Inter-Integrated Circuit Interface (I
2
C) timing
Table 46. I
2
C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency f
SCL
0 100 0 400 kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
t
HD
; STA 4 — 0.6 — µs
LOW period of the SCL clock t
LOW
4.7 — 1.3 — µs
HIGH period of the SCL clock t
HIGH
4 — 0.6 — µs
Set-up time for a repeated START
condition
t
SU
; STA 4.7 — 0.6 — µs
Data hold time for I
2
C bus devices t
HD
; DAT 0
1
3.45
2
0
3
0.9
1
µs
Data set-up time t
SU
; DAT 250
4
— 100
2, 5
— ns
Rise time of SDA and SCL signals t
r
— 1000 20 +0.1C
b
6
300 ns
Fall time of SDA and SCL signals t
f
— 300 20 +0.1C
b
5
300 ns
Set-up time for STOP condition t
SU
; STO 4 — 0.6 — µs
Bus free time between STOP and
START condition
t
BUF
4.7 — 1.3 — µs
Pulse width of spikes that must be
suppressed by the input filter
t
SP
N/A N/A 0 50 ns
1. The master mode I
2
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10ns and Output Load = 50pf
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I
2
C bus device can be used in a Standard mode I2C bus system, but the requirement t
SU; DAT
≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t
rmax
+ t
SU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I
2
C bus specification) before the SCL line is released.
Peripheral operating requirements and behaviors
K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
62 Freescale Semiconductor, Inc.