Datasheet

6. C
b
= total capacitance of the one bus line in pF.


SDA
SCL
t
HD; STA
t
HD; DAT
t
LOW
t
SU; DAT
t
HIGH
t
SU; STA
SR
P
S
S
t
HD; STA
t
SP
t
SU; STO
t
BUF
t
f
t
r
t
f
t
r
Figure 26. Timing definition for fast and standard mode devices on the I
2
C bus
6.8.9 UART switching specifications
See General switching specifications.
6.8.10 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 47. SDHC switching specifications
Num Symbol Description Min. Max. Unit
Card input clock
SD1 fpp Clock frequency (low speed) 0 400 kHz
fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz
fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz
f
OD
Clock frequency (identification mode) 0 400 kHz
SD2 t
WL
Clock low time 7 — ns
SD3 t
WH
Clock high time 7 — ns
SD4 t
TLH
Clock rise time — 3 ns
SD5 t
THL
Clock fall time — 3 ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6 t
OD
SDHC output delay (output valid) -5 8.3 ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7 t
ISU
SDHC input setup time 5 — ns
SD8 t
IH
SDHC input hold time 0 — ns
Peripheral operating requirements and behaviors
K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 63