Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller MAPBGA 144 (13x13) 32-Bit 150 MHz I/O number 100

K60P144M150SF3

K60 Sub-Family

Supports the following:

MK60FX512VLQ15,

MK60FN1M0VLQ15,

MK60FX512VMD15,

MK60FN1M0VMD15

Key features

• Operating Characteristics

– Voltage range: 1.71 to 3.6 V

– Flash write voltage range: 1.71 to 3.6 V

– Temperature range (ambient): -40 to 105°C

• Performance

– Up to 150 MHz ARM Cortex-M4 core with DSP

instructions delivering 1.25 Dhrystone MIPS per

MHz

• Memories and memory interfaces

– Up to 1024 KB program flash memory on non-

FlexMemory devices

– Up to 512 KB program flash memory on

FlexMemory devices

– Up to 512 KB FlexNVM on FlexMemory devices

– 16 KB FlexRAM on FlexMemory devices

– Up to 128 KB RAM

– Serial programming interface (EzPort)

– FlexBus external bus interface

– NAND flash controller interface

• Clocks

– 3 to 32 MHz crystal oscillator

– 32 kHz crystal oscillator

– Multi-purpose clock generator

• System peripherals

– Multiple low-power modes to provide power

optimization based on application requirements

– Memory protection unit with multi-master

protection

– 32-channel DMA controller, supporting up to

128 request sources

– External watchdog monitor

– Software watchdog

– Low-leakage wakeup unit

• Security and integrity modules

– Hardware CRC module to support fast cyclic

redundancy checks

– Hardware random-number generator

– Hardware encryption supporting DES, 3DES,

AES, MD5, SHA-1, and SHA-256 algorithms

– 128-bit unique identification (ID) number per

chip

• Human-machine interface

– Low-power hardware touch sensor interface

(TSI)

– General-purpose input/output

• Analog modules

– Four 16-bit SAR ADCs

– Programmable gain amplifier (PGA) (up to x64)

integrated into each ADC

– Two 12-bit DACs

– Four analog comparators (CMP) containing a 6-

bit DAC and programmable reference input

– Voltage reference

• Timers

– Programmable delay block

– Two 8-channel motor control/general purpose/

PWM timers

– Two 2-channel quadrature decoder/general

purpose timers

– IEEE 1588 timers

– Periodic interrupt timers

– 16-bit low-power timer

– Carrier modulator transmitter

– Real-time clock

Freescale Semiconductor

Document Number K60P144M150SF3

Data Sheet: Technical Data

Rev 5, 10/2013

Freescale reserves the right to change the detail specifications as may be

required to permit improvements in the design of its products.

Summary of content (94 pages)

PAGE 1
Freescale Semiconductor Data Sheet: Technical Data K60 Sub-Family Document Number K60P144M150SF3 Rev 5, 10/2013 K60P144M150SF3 Supports the following: MK60FX512VLQ15, MK60FN1M0VLQ15, MK60FX512VMD15, MK60FN1M0VMD15 Key features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C • Performance – Up to 150 MHz ARM Cortex-M4 core with DSP instructions delivering 1.
PAGE 2
• Communication interfaces – Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability – USB high-/full-/low-speed On-the-Go controller with ULPI interface – USB high-/full-/low-speed On-the-Go controller with on-chip high speed transceiver – USB full-/low-speed On-the-Go controller with on-chip transceiver – USB Device Charger detect – Two Controller Area Network (CAN) modules – Three SPI modules – Two I2C modules – Six UART modules – Secure Digital host controller (
PAGE 3
Table of Contents 1 Ordering parts...........................................................................5 5.4.2 Thermal attributes...............................................24 1.1 Determining valid orderable parts......................................5 5.5 Power sequencing.............................................................24 2 Part identification......................................................................5 6 Peripheral operating requirements and behaviors..................
PAGE 4
6.9.1 TSI electrical specifications................................76 8.2 K60 Signal Multiplexing and Pin Assignments..................78 7 Dimensions...............................................................................77 8.3 K61 Signal Multiplexing and Pin Assignments..................84 7.1 Obtaining package dimensions.........................................77 8.4 K60 pinouts.......................................................................90 8 Pinout................................
PAGE 5
Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: PK60 and MK60 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.
PAGE 6
Terminology and guidelines Field Description Values T Temperature range (°C) • V = –40 to 105 • C = –40 to 85 PP Package identifier • LQ = 144 LQFP (20 mm x 20 mm) • MD = 144 MAPBGA (13 mm x 13 mm) • MJ = 256 MAPBGA (17 mm x 17 mm) CC Maximum CPU frequency (MHz) • 15 = 150 MHz N Packaging type • R = Tape and reel • (Blank) = Trays 2.4 Example This is an example part number: MK60FN1M0VLQ15 3 Terminology and guidelines 3.
PAGE 7
Terminology and guidelines 3.2.1 Example This is an example of an operating behavior: Symbol IWP Description Min. Digital I/O weak pullup/ 10 pulldown current Max. 130 Unit µA 3.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins Min. — Max. 7 Unit pF 3.
PAGE 8
Terminology and guidelines 3.5 Result of exceeding a rating 40 Failures in time (ppm) 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic 3.6 Relationship between ratings and operating requirements g( Op era tin g in rat ) in. m m ire g tin era Op u req t en in. (m ) m ire Op g tin era u req t en (m ax .) x.
PAGE 9
Terminology and guidelines • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.
PAGE 10
Ratings 5000 4500 4000 TJ IDD_STOP (μA) 3500 150 °C 3000 105 °C 2500 25 °C 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 VDD (V) 3.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max.
PAGE 11
Ratings 4.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol Description Min. Max.
PAGE 12
General 2. It covers digital pins. 3. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 5 General 5.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 1. Input signal measurement reference All digital I/O switching characteristics assume: 1.
PAGE 13
General Table 1. Voltage and current operating requirements (continued) Symbol Description Min. Max. Unit RTC battery supply voltage 1.71 3.6 V • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V • 2.7 V ≤ VDD ≤ 3.6 V — 0.35 × VDD V • 1.7 V ≤ VDD ≤ 2.7 V — 0.3 × VDD V VHYS Input hysteresis (digital pins) 0.06 × VDD — V IICDIO Digital pin negative DC injection current — single pin -5 — mA • VIN < VSS-0.
PAGE 14
General Table 2. LVD and POR operating requirements (continued) Symbol Description Min. Typ. Max. Unit — ±80 — mV 1.54 1.60 1.66 V 1.74 1.80 1.86 V 1.84 1.90 1.96 V 1.94 2.00 2.06 V 2.04 2.10 2.
PAGE 15
General Table 4. Voltage and current operating behaviors (continued) Symbol Description • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA Min. Typ. Max. Unit — — 0.5 V 0.5 V 0.5 V Notes • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 5 mA Output low voltage — low drive strength IOLT IOLT_io60 IINA — • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA — • 1.71 V ≤ VDD ≤ 2.
PAGE 16
General 2. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL. 3. Internal pull-up/pull-down resistors disabled. 4. Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V. See Figure 1. 5. Measured at VDD supply voltage = VDD min and Vinput = VSS 6.
PAGE 17
General Table 5. Power mode transition operating behaviors (continued) Symbol Description • LLS → RUN • VLPS → RUN • STOP → RUN Min. Max. Unit — 5.0 μs — 5 μs — 4.8 μs Notes 1. Normal boot (FTFE_FOPT[LPBOOT]=1) 5.2.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol IDDA IDD_RUN IDD_RUN Description Min. Typ. Max. Unit Notes — — See note mA 1 • @ 1.8V — 59.6 180 mA • @ 3.0V — 59.6 185 mA • @ 1.8V — 89.9 205 mA • @ 3.
PAGE 18
General Table 6. Power consumption operating behaviors (continued) Symbol Description IDD_LLS Low leakage stop mode current at 3.0 V IDD_VLLS3 IDD_VLLS2 IDD_VLLS1 IDD_VBAT Min. Typ. Max. Unit • @ –40 to 25°C — 0.25 1.3 mA • @ 70°C — 0.85 7.6 mA • @ 105°C — 2.4 12.54 mA Very low-leakage stop mode 3 current at 3.0 V Notes 6 • @ –40 to 25°C — 5.6 20 μA • @ 70°C — 30.1 137 μA • @ 105°C — 120.8 246 μA • @ –40 to 25°C — 3.2 14 μA • @ 70°C — 11.
PAGE 19
General • No GPIOs toggled • Code execution from flash with cache enabled • For the ALLOFF curve, all peripheral clocks are disabled except FTFE Figure 3. Run mode supply current vs. core frequency K60 Sub-Family, Rev5, 10/2013. Freescale Semiconductor, Inc.
PAGE 20
General Figure 4. VLPR mode supply current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors for 256MAPBGA Symbol Description Frequency band (MHz) Typ. Unit Notes ,, VRE1 Radiated emissions voltage, band 1 0.15–50 21 dBμV VRE2 Radiated emissions voltage, band 2 50–150 24 dBμV VRE3 Radiated emissions voltage, band 3 150–500 29 dBμV VRE4 Radiated emissions voltage, band 4 500–1000 28 dBμV 5.2.
PAGE 21
General 1. Go to www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.8 Capacitance attributes Table 8. Capacitance attributes Symbol Description Min. Max. Unit CIN_A Input capacitance: analog pins — 7 pF CIN_D Input capacitance: digital pins — 7 pF Input capacitance: fast digital pins — 9 pF CIN_D_io60 5.3 Switching specifications 5.3.1 Device clock specifications Table 9. Device clock specifications Symbol Description Min. Max.
PAGE 22
General 5.3.2 General switching specifications These general purpose specifications apply to all pins configured for: • GPIO signaling • Other peripheral module signaling not explicitly stated elsewhere Table 10. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.
PAGE 23
General Table 10. General switching specifications (continued) Symbol Description Min. Max. Unit Notes • 1.71 ≤ VDD ≤ 2.7V — 18 ns — • 2.7 ≤ VDD ≤ 3.6V — 9 ns — • 1.71 ≤ VDD ≤ 2.7V — 48 ns — • 2.7 ≤ VDD ≤ 3.6V — 24 ns — • Slew enabled tio60 6 Port rise and fall time (high drive strength) • Slew disabled • 1.71 ≤ VDD ≤ 2.7V — 6 ns — • 2.7 ≤ VDD ≤ 3.6V — 3 ns — • 1.71 ≤ VDD ≤ 2.7V — 28 ns — • 2.7 ≤ VDD ≤ 3.
PAGE 24
General 5.4.2 Thermal attributes Board type Symbol Description 144 LQFP 144 MAPBGA Unit Notes Single-layer (1s) RθJA Thermal 45 resistance, junction to ambient (natural convection) 50 °C/W Four-layer (2s2p) RθJA Thermal 36 resistance, junction to ambient (natural convection) 30 °C/W 1 Single-layer (1s) RθJMA Thermal 36 resistance, junction to ambient (200 ft./ min. air speed) 41 °C/W 1 Four-layer (2s2p) RθJMA Thermal 30 resistance, junction to ambient (200 ft./ min.
PAGE 25
Peripheral operating requirements and behaviors 2. VDD_INT 3. VDDA 4. VDD_DDR The power-down sequence is the reverse: 1. 2. 3. 4. VDD_DDR VDDA VDD_INT VDD 6 Peripheral operating requirements and behaviors 6.1 Core modules 6.1.1 Debug trace timing specifications Table 12. Debug trace operating behaviors Symbol Description Min. Max.
PAGE 26
Peripheral operating requirements and behaviors TRACE_CLKOUT Ts Th Ts Th TRACE_D[3:0] Figure 6. Trace data specifications 6.1.2 JTAG electricals Table 13. JTAG limited voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 2.7 3.
PAGE 27
Peripheral operating requirements and behaviors Table 14. JTAG full voltage range electricals (continued) Symbol Description Min. Max. • Boundary Scan 0 10 • JTAG and CJTAG 0 20 • Serial Wire Debug 0 40 1/J1 — ns • Boundary Scan 50 — ns • JTAG and CJTAG 25 — ns • Serial Wire Debug 12.
PAGE 28
Peripheral operating requirements and behaviors TCLK J5 Data inputs J6 Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 8. Boundary scan (JTAG) timing TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 9. Test Access Port timing K60 Sub-Family, Rev5, 10/2013. 28 Freescale Semiconductor, Inc.
PAGE 29
Peripheral operating requirements and behaviors TCLK J14 J13 TRST Figure 10. TRST timing 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules 6.3.1 MCG specifications Table 15. MCG specifications Symbol Description Min. Typ. Max. Unit — 32.768 — kHz 31.25 — 39.0625 kHz Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM — ± 0.3 ± 0.
PAGE 30
Peripheral operating requirements and behaviors Table 15. MCG specifications (continued) Symbol fdco Description DCO output frequency range Low range (DRS=00) Min. Typ. Max. Unit Notes 20 20.97 25 MHz 2, 3 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz — 23.99 — MHz — 47.97 — MHz — 71.99 — MHz — 95.
PAGE 31
Peripheral operating requirements and behaviors Table 15. MCG specifications (continued) Symbol Jacc_pll Description Min. Typ. Max. Unit • fvco = 180 MHz — 100 — ps • fvco = 360 MHz — 75 — ps • fvco = 180 MHz — 600 — ps • fvco = 360 MHz — 300 — ps Notes PLL accumulated jitter over 1µs (RMS) 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2.
PAGE 32
Peripheral operating requirements and behaviors Table 16. Oscillator DC electrical specifications (continued) Symbol Description Min. Typ. Max.
PAGE 33
Peripheral operating requirements and behaviors Table 17. Oscillator frequency specifications (continued) Symbol Description Min. Typ. Max.
PAGE 34
Peripheral operating requirements and behaviors 6.3.3.2 Symbol fosc_lo tstart 32 kHz oscillator frequency specifications Table 19. 32 kHz oscillator frequency specifications Description Min. Typ. Max. Unit Oscillator crystal — 32.768 — kHz Crystal start-up time — 1000 — ms 700 — VBAT mV vec_extal32 Externally provided input clock amplitude Notes 3 1. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply.
PAGE 35
Peripheral operating requirements and behaviors Table 21. Flash command timing specifications (continued) Symbol Description Min. Typ. Max.
PAGE 36
Peripheral operating requirements and behaviors Table 21. Flash command timing specifications (continued) Symbol Description Min. Typ. Max.
PAGE 37
Peripheral operating requirements and behaviors Table 23. NVM reliability specifications (continued) Min. Typ.1 Max.
PAGE 38
Peripheral operating requirements and behaviors • EEESIZE — allocated FlexRAM based on DEPART; entered with Program Partition command • Write_efficiency — • 0.25 for 8-bit writes to FlexRAM • 0.50 for 16-bit or 32-bit writes to FlexRAM • nnvmcycee — EEPROM-backup cycling endurance Figure 11. EEPROM backup writes to FlexRAM 6.4.2 EzPort switching specifications Table 24. EzPort switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.
PAGE 39
Peripheral operating requirements and behaviors Table 24. EzPort switching specifications (continued) Num Description Min. Max.
PAGE 40
Peripheral operating requirements and behaviors The SCALER value is derived from the fractional divider specified in the SIM's CLKDIV4 register: SCALER = SIM_CLKDIV4[NFCFRAC] + 1 SIM_CLKDIV4[NFCDIV] + 1 In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%, means TH = TL. In case the reciprocal of SCALER is not an integer: T L = (1 + SCALER / 2) x T H = (1 – SCALER / 2) x T NFC 2 T NFC 2 For example, if SCALER is 0.2, then TH = TL = TNFC/2.
PAGE 41
Peripheral operating requirements and behaviors Table 25. NFC specifications (continued) Num Description Min. Max. Unit tRR Ready to NFC_RE low 4TH + 3TL + 90 — ns tRP NFC_RE pulse width TL + 1 — ns tRC Read cycle time TL + TH – 1 — ns tREH NFC_RE high hold time TH – 1 — ns tIS Data input setup time 11 — ns NFC_CLE tCLS tCLH NFC_CEn tCS tWP tCH NFC_WE tDS tDH NFC_IOn Figure 13.
PAGE 42
Peripheral operating requirements and behaviors tCS tCH tWC NFC_CEn tWP tWH tDS tDH NFC_WE NFC_IOn data data data Figure 15. Write data latch cycle timing tCH tRC NFC_CEn tREH tRP NFC_RE tIS NFC_IOn data data data tRR NFC_RB Figure 16. Read data latch cycle timing in non-fast mode tCH tRC NFC_CEn tRP tREH NFC_RE tIS NFC_IOn data data data tRR NFC_RB Figure 17. Read data latch cycle timing in fast mode 6.4.
PAGE 43
Peripheral operating requirements and behaviors The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 26. Flexbus limited voltage range switching specifications Num Description Min. Max. Unit Operating voltage 2.7 3.6 V Frequency of operation — FB_CLK MHz FB1 Clock period 20 — ns FB2 Address, data, and control output valid — 11.
PAGE 44
Peripheral operating requirements and behaviors FB1 FB_CLK FB3 FB5 FB_A[Y] Address FB4 FB2 FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 18. FlexBus read timing diagram K60 Sub-Family, Rev5, 10/2013. 44 Freescale Semiconductor, Inc.
PAGE 45
Peripheral operating requirements and behaviors FB1 FB_CLK FB2 FB3 FB_A[Y] FB_D[X] Address Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 19. FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K60 Sub-Family, Rev5, 10/2013. Freescale Semiconductor, Inc.
PAGE 46
Peripheral operating requirements and behaviors 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 28 and Table 29 are achievable on the differential pins ADCx_DP0, ADCx_DM0. The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are not direct device pins. Accuracy specifications for these pins are defined in Table 30 and Table 31. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.
PAGE 47
Peripheral operating requirements and behaviors Table 28. 16-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU.
PAGE 48
Peripheral operating requirements and behaviors Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description Conditions1. • ADLPC = 0, ADHSC = 0 Min. Typ. Max. 4.4 6.2 9.5 TUE DNL INL EFS EQ ENOB See Reference Manual chapter for sample times Total unadjusted error • 12-bit modes — ±4 ±6.8 • <12-bit modes — ±1.4 ±2.1 Differential nonlinearity • 12-bit modes — ±0.7 –1.1 to +1.9 • <12-bit modes — ±0.2 • 12-bit modes — ±1.
PAGE 49
Peripheral operating requirements and behaviors Table 29. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description Conditions1. Min. Typ. Max. Unit Notes (refer to the MCU's voltage and current operating ratings) VTEMP25 Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C Temp sensor voltage 25 °C 706 716 726 mV 6 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2.
PAGE 50
Peripheral operating requirements and behaviors Figure 22. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 6.6.1.3 16-bit ADC with PGA operating conditions Table 30. 16-bit ADC with PGA operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 — 3.
PAGE 51
Peripheral operating requirements and behaviors Table 30. 16-bit ADC with PGA operating conditions (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes 16 bit modes 37.037 — 250 Ksps 8 No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2.
PAGE 52
Peripheral operating requirements and behaviors Table 31. 16-bit ADC with PGA characteristics (continued) Min. Typ.1 Max. Unit Notes — -84 — dB VDDA= 3V ±100mV, fVDDA= 50Hz, 60Hz • Gain=1 — -84 — dB • Gain=64 — -85 — dB VCM= 500mVpp, fVCM= 50Hz, 100Hz • Chopping disabled (ADC_PGA[PGACHPb] =1) • Chopping enabled (ADC_PGA[PGACHPb] =0) — 2.4 — mV — 0.2 — mV — — 10 µs • Gain=1 • Gain=64 — 6 10 ppm/°C — 31 42 ppm/°C • Gain=1 • Gain=64 — 0.07 0.21 %/V — 0.14 0.
PAGE 53
Peripheral operating requirements and behaviors Table 31. 16-bit ADC with PGA characteristics (continued) Symbol SINAD Description Signal-to-noise plus distortion ratio Min. Typ.1 Max. Unit • Gain=64, Average=8 6.3 9.6 — bits • Gain=1, Average=32 12.8 14.5 — bits • Gain=2, Average=32 11.0 14.3 — bits • Gain=4, Average=32 7.9 13.8 — bits • Gain=8, Average=32 7.3 13.1 — bits • Gain=16, Average=32 6.8 12.5 — bits • Gain=32, Average=32 6.8 11.
PAGE 54
Peripheral operating requirements and behaviors Table 32. Comparator and 6-bit DAC electrical specifications (continued) Symbol IDAC6b Description Min. Typ. Max. Unit Analog comparator initialization delay2 — — 40 μs 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2.
PAGE 55
Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP P Hystereris (V) 0.12 HYSTCTR Setting 0.1 00 01 0 08 0.08 10 11 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 Vin level (V) 1.9 2.2 2.5 2.8 3.1 Figure 24. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) 6.6.3 12-bit DAC electrical characteristics 6.6.3.1 Symbol 12-bit DAC operating requirements Table 33. 12-bit DAC operating requirements Desciption Min. Max. Unit VDDA Supply voltage 1.71 3.
PAGE 56
Peripheral operating requirements and behaviors 6.6.3.2 Symbol 12-bit DAC operating behaviors Table 34. 12-bit DAC operating behaviors Description IDDA_DACL Supply current — low-power mode Min. Typ. Max. Unit — — 150 μA — — 700 μA Notes P IDDA_DACH Supply current — high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) — low-power mode — 100 200 μs tDACHP Full-scale settling time (0x080 to 0xF7F) — high-power mode — 15 30 μs 1 — 0.
PAGE 57
Peripheral operating requirements and behaviors Figure 25. Typical INL error vs. digital code K60 Sub-Family, Rev5, 10/2013. Freescale Semiconductor, Inc.
PAGE 58
Peripheral operating requirements and behaviors Figure 26. Offset at half scale vs. temperature 6.6.4 Voltage reference electrical specifications Table 35. VREF full-range operating requirements Symbol Description Min. Max. Unit VDDA Supply voltage 1.71 3.6 V TA Temperature CL Output load capacitance Operating temperature range of the device °C 100 nF Notes 1, 2 1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external reference.
PAGE 59
Peripheral operating requirements and behaviors Table 36. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes Vout Voltage reference output with factory trim at nominal VDDA and temperature=25C 1.1915 1.195 1.1977 V 1 Vout Voltage reference output — factory trim 1.1584 — 1.2376 V 1 Vout Voltage reference output — user trim 1.193 — 1.197 V 1 Vstep Voltage reference trim step — 0.
PAGE 60
Peripheral operating requirements and behaviors 6.8.1 Ethernet switching specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 6.8.1.1 MII signal switching specifications The following timing specs meet the requirements for MII style interfaces for a range of transceiver devices. Table 39. MII signal switching specifications Symbol — Description Min. RXCLK frequency Max.
PAGE 61
Peripheral operating requirements and behaviors MII2 MII1 MII3 MII4 RXCLK (input) RXD[n:0] Valid data RXDV Valid data RXER Valid data Figure 28. RMII/MII receive signal timing diagram 6.8.1.2 RMII signal switching specifications The following timing specs meet the requirements for RMII style interfaces for a range of transceiver devices. Table 40. RMII signal switching specifications Num — Description EXTAL frequency (RMII input clock RMII_CLK) Min. Max.
PAGE 62
Peripheral operating requirements and behaviors 6.8.3 USB DCD electrical specifications Table 41. USB DCD electrical specifications Symbol Description Min. Typ. Max. Unit VDP_SRC USB_DP source voltage (up to 250 μA) 0.5 — 0.7 V Threshold voltage for logic high 0.8 — 2.0 V 7 10 13 μA VLGC IDP_SRC USB_DP source current IDM_SINK USB_DM sink current 50 100 150 μA RDM_DWN D- pulldown resistance for data pin contact detect 14.25 — 24.8 kΩ VDAT_REF Data detect voltage 0.25 0.
PAGE 63
Peripheral operating requirements and behaviors 6.8.5 ULPI timing specifications The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin Interface. Control and data timing requirements for the ULPI pins are given in the following table. These timings apply to synchronous mode only. All timings are measured with respect to the clock as seen at the USB_CLKIN pin. Table 43. ULPI timing specifications Num Description Min. Typ. Max.
PAGE 64
Peripheral operating requirements and behaviors 6.8.6 CAN switching specifications See General switching specifications. 6.8.7 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes.
PAGE 65
Peripheral operating requirements and behaviors Table 45. Slave mode DSPI timing (limited voltage range) Num Description Min. Max. Unit 2.7 3.
PAGE 66
Peripheral operating requirements and behaviors Table 46. Master mode DSPI timing (full voltage range) (continued) Num Description Min. Max. Unit Notes DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) − 4 — ns 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) − 4 — ns 3 DS5 DSPI_SCK to DSPI_SOUT valid — 10 ns DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 — ns DS7 DSPI_SIN to DSPI_SCK input setup 20.
PAGE 67
Peripheral operating requirements and behaviors DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Last data Data DS14 First data Data Last data Figure 33. DSPI classic SPI timing — slave mode 6.8.9 Inter-Integrated Circuit Interface (I2C) timing Table 48. I 2C timing Characteristic Symbol Standard Mode Fast Mode Unit Minimum Maximum Minimum Maximum SCL Clock Frequency fSCL 0 100 0 400 kHz Hold time (repeated) START condition.
PAGE 68
Peripheral operating requirements and behaviors SDA tf tLOW tSU; DAT tr tf tHD; STA tr tSP tBUF SCL S tHD; STA tHD; DAT tHIGH tSU; STA tSU; STO SR P S Figure 34. Timing definition for fast and standard mode devices on the I2C bus 6.8.10 UART switching specifications See General switching specifications. 6.8.
PAGE 69
Peripheral operating requirements and behaviors Table 50. SDHC switching specifications over the full operating voltage range Num Symbol Description Min. Max. Unit Operating voltage 1.71 3.
PAGE 70
Peripheral operating requirements and behaviors is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the frame sync (FS) signal shown in the following figures. 6.8.12.1 Normal Run, Wait and Stop mode performance over a limited operating voltage range This section provides the operating performance over a limited operating voltage for the device in Normal Run, Wait and Stop modes.
PAGE 71
Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 36. I2S/SAI timing — master modes Table 52. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage range) Num. Characteristic Min. Max. Unit Operating voltage 2.7 3.
PAGE 72
Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 37. I2S/SAI timing — slave modes 6.8.12.2 Normal Run, Wait and Stop mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. Table 53.
PAGE 73
Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 38. I2S/SAI timing — master modes Table 54. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.
PAGE 74
Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 39. I2S/SAI timing — slave modes 6.8.12.3 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. Table 55.
PAGE 75
Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_TX_BCLK/ I2S_RX_BCLK (output) S4 S4 S6 S5 I2S_TX_FS/ I2S_RX_FS (output) S10 S9 I2S_TX_FS/ I2S_RX_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 40. I2S/SAI timing — master modes Table 56. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.
PAGE 76
Peripheral operating requirements and behaviors S11 S12 I2S_TX_BCLK/ I2S_RX_BCLK (input) S12 S15 S16 I2S_TX_FS/ I2S_RX_FS (output) S13 I2S_TX_FS/ I2S_RX_FS (input) S19 S14 S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 41. I2S/SAI timing — slave modes 6.9 Human-machine interfaces (HMI) 6.9.1 TSI electrical specifications Table 57. TSI electrical specifications Symbol Description Min. Typ. Max. Unit VDDTSI Operating voltage 1.71 — 3.
PAGE 77
Dimensions 1. 2. 3. 4. 5. 6. 7. 8. 9. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. Fixed external capacitance of 20 pF. REFCHRG = 2, EXTCHRG=0. REFCHRG = 0, EXTCHRG = 10. VDD = 3.0 V. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
PAGE 78
Pinout Table 58. Pins with active pull control after reset Pin Active pull direction after reset PTA0 pulldown PTA1 pullup PTA3 pullup PTA4 pullup RESET_b pullup 8.2 K60 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin.
PAGE 79
Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 14 G4 PTE11 ADC3_SE16 ADC3_SE16 PTE11 15 G3 PTE12 ADC3_SE17 ADC3_SE17 PTE12 16 E6 VDD VDD VDD 17 F7 VSS VSS VSS 18 H3 VSS VSS VSS 19 H1 USB0_DP USB0_DP USB0_DP 20 H2 USB0_DM USB0_DM USB0_DM 21 G1 VOUT33 VOUT33 VOUT33 22 G2 VREGIN VREGIN VREGIN 23 J1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 24 J2 PGA2_DM/ ADC2_DM0/ ADC3_DM3/
PAGE 80
Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 36 J3 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 37 M3 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 38 L3 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 39 L4 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP
PAGE 81
Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 59 J8 PTA7 ADC0_SE10 ADC0_SE10 PTA7 ULPI_DIR FTM0_CH4 I2S1_RX_ BCLK 60 K8 PTA8 ADC0_SE11 ADC0_SE11 PTA8 ULPI_NXT FTM1_CH0 I2S1_RX_FS FTM1_QD_ PHA TRACE_D2 61 L8 PTA9 ADC3_SE5a ADC3_SE5a PTA9 ULPI_STP FTM1_CH1 MII0_RXD3 FTM1_QD_ PHB TRACE_D1 62 M9 PTA10 ADC3_SE4a ADC3_SE4a PTA10 ULPI_DATA0 FTM2_CH0 MII0_RXD2 FTM2_QD_ PHA TRACE_D0 63 L9 PTA11 ADC3_SE15 ADC3_SE15 PTA11
PAGE 82
Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 83 G12 PTB2 ADC0_SE12/ TSI0_CH7 ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCL UART0_RTS_ ENET0_1588_ b TMR0 FTM0_FLT3 84 G11 PTB3 ADC0_SE13/ TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDA UART0_CTS_ ENET0_1588_ b/ TMR1 UART0_COL_ b FTM0_FLT0 85 G10 PTB4 ADC1_SE10 ADC1_SE10 PTB4 ENET0_1588_ TMR2 FTM1_FLT0 86 G9 PTB5 ADC1_SE11 ADC1_SE11 PTB5 ENET0_1588_ TMR3 FTM2_FLT0 87 F12 PTB6 ADC1_SE12 ADC1_SE12
PAGE 83
Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 109 A9 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11/ NFC_DATA8 CMP1_OUT I2S1_TX_ BCLK 110 D8 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 I2S0_RXD0 FB_AD10/ NFC_DATA7 CMP0_OUT I2S1_TX_FS 111 C8 PTC6/ LLWU_P10 CMP0_IN0 CMP0_IN0 PTC6/ LLWU_P10 SPI0_SOUT PDB0_EXTRG I2S0_RX_ BCLK FB_AD9/ NFC_DATA6 I2S0_MCLK 112 B8 PTC7 CMP0_IN1 CMP0_IN1 PT
PAGE 84
Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 132 A3 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_ FTM0_CH5 b/ UART0_COL_ b FB_AD1/ NFC_DATA0 EWM_OUT_b 133 A2 PTD6/ LLWU_P15 ADC0_SE7b ADC0_SE7b PTD6/ LLWU_P15 SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0 134 M10 VSS VSS VSS 135 F8 VDD VDD VDD 136 A1 PTD7 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 137 C9 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16/ NFC_CLE 138 B9 PTD
PAGE 85
Pinout 144 MAP BGA Pin Name Default ALT0 ALT1 F4 PTE7 DISABLED F3 PTE8 ADC2_SE16 ADC2_SE16 PTE8 F2 PTE9 ADC2_SE17 ADC2_SE17 PTE9 ALT2 PTE7 ALT3 ALT4 ALT5 ALT6 UART3_RTS_b I2S0_RXD0 FTM3_CH2 I2S0_RXD1 UART5_TX I2S0_RX_FS FTM3_CH3 I2S0_TXD1 UART5_RX I2S0_RX_BCLK FTM3_CH4 F1 PTE10 DISABLED PTE10 UART5_CTS_b I2S0_TXD0 FTM3_CH5 G4 PTE11 ADC3_SE16 ADC3_SE16 PTE11 UART5_RTS_b I2S0_TX_FS FTM3_CH6 G3 PTE12 ADC3_SE17 ADC3_SE17 PTE12 E6 VDD VDD VDD F7 VSS VSS
PAGE 86
Pinout 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort K3 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 J3 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 M3 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 L3 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0
PAGE 87
Pinout 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 K8 PTA8 ADC0_SE11 ADC0_SE11 PTA8 ULPI_NXT FTM1_CH0 I2S1_RX_FS FTM1_QD_ PHA TRACE_D2 L8 PTA9 ADC3_SE5a ADC3_SE5a PTA9 ULPI_STP FTM1_CH1 MII0_RXD3 FTM1_QD_ PHB TRACE_D1 M9 PTA10 ADC3_SE4a ADC3_SE4a PTA10 ULPI_DATA0 FTM2_CH0 MII0_RXD2 FTM2_QD_ PHA TRACE_D0 L9 PTA11 ADC3_SE15 ADC3_SE15 PTA11 ULPI_DATA1 FTM2_CH1 MII0_RXCLK FTM2_QD_ PHB K9 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_C
PAGE 88
Pinout 144 MAP BGA Pin Name Default ALT0 ALT1 G11 PTB3 ADC0_SE13/ TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 G10 PTB4 ADC1_SE10 ADC1_SE10 G9 PTB5 ADC1_SE11 F12 PTB6 F11 PTB7 F10 PTB8 DISABLED PTB8 F9 PTB9 DISABLED PTB9 E12 PTB10 ADC1_SE14 ADC1_SE14 E11 PTB11 ADC1_SE15 ADC1_SE15 H7 VSS VSS VSS F5 VDD VDD VDD E10 PTB16 TSI0_CH9 E9 PTB17 TSI0_CH10 D12 PTB18 D11 ALT2 I2C0_SDA ALT3 ALT4 ALT5 ALT6 UART0_CTS_ ENET0_1588_ b/ TMR1 UART0_COL_b FTM0_FLT0 PTB4 ENET0
PAGE 89
Pinout 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 SPI0_SIN USB_SOF_ OUT I2S0_RX_FS FB_AD8/ NFC_DATA5 FB_AD7/ NFC_DATA4 ALT6 B8 PTC7 CMP0_IN1 CMP0_IN1 PTC7 A8 PTC8 ADC1_SE4b/ CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 FTM3_CH4 I2S0_MCLK D7 PTC9 ADC1_SE5b/ CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 FTM3_CH5 I2S0_RX_BCLK FB_AD6/ NFC_DATA3 FTM2_FLT0 C7 PTC10 ADC1_SE6b ADC1_SE6b PTC10 I2C1_SCL FTM3_CH6 I2S0_RX_FS FB_AD5/ NFC_DATA2 I2S1_MCLK B7 PTC11/ LLWU_P11 ADC1_SE7b
PAGE 90
Pinout 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 UART5_RTS_b ALT5 ALT6 B3 PTD10 DISABLED PTD10 B2 PTD11 DISABLED PTD11 SPI2_PCS0 UART5_CTS_b SDHC0_CLKIN FB_A19 B1 PTD12 DISABLED PTD12 SPI2_SCK FTM3_FLT0 SDHC0_D4 FB_A20 C3 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21 C2 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22 C1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23 M5 NC NC NC A10 NC NC NC B10 NC NC NC C10 NC NC NC ALT7 EzPort
PAGE 91
PTD15 PTD14 PTD13 PTD12 PTD11 PTD10 PTD9 PTD8 PTD7 VDD VSS PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2/LLWU_P13 PTD1 PTD0/LLWU_P12 PTC19 PTC18 PTC17 PTC16 VDD VSS PTC15 PTC14 PTC13 PTC12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 Pinout PTE0 1 108 VDD PTE1/LL
PAGE 92
Revision History 1 2 3 4 5 6 7 8 9 10 11 12 A PTD7 PTD6/ LLWU_P15 PTD5 PTD4/ LLWU_P14 PTD0/ LLWU_P12 PTC16 PTC12 PTC8 PTC4/ LLWU_P8 NC PTC3/ LLWU_P7 PTC2 A B PTD12 PTD11 PTD10 PTD3 PTC19 PTC15 PTC11/ LLWU_P11 PTC7 PTD9 NC PTC1/ LLWU_P6 PTC0 B C PTD15 PTD14 PTD13 PTD2/ LLWU_P13 PTC18 PTC14 PTC10 PTC6/ LLWU_P10 PTD8 NC PTB23 PTB22 C D PTE2/ LLWU_P1 PTE1/ LLWU_P0 PTE0 PTD1 PTC17 PTC13 PTC9 PTC5/ LLWU_P9 PTB21 PTB20 PTB19 PTB18 D E PTE6 PTE5
PAGE 93
Revision History Table 59. Revision History (continued) Rev. No. Date Substantial Changes 4 10/2012 Replaced TBDs throughout. 5 10/2013 Changes for 4N96B mask set: • Min VDD operating requirement specification updated to support operation down to 1.71V. New specifications: • Added Vodpu specification. • Removed Ioz, Ioz_ddr, and Ioz_tamper Hi-Z leakage specficiations. They have been replaced by new Iina, Iind, and Zind specifications. • Fpll_ref_acc specification has been added.
PAGE 94
How to Reach Us: Information in this document is provided solely to enable system and software Home Page: freescale.com implementers to use Freescale products. There are no express or implied copyright Web Support: freescale.com/support information in this document. licenses granted hereunder to design or fabricate any integrated circuits based on the Freescale reserves the right to make changes without further notice to any products herein.