Datasheet

2. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
3. Internal pull-up/pull-down resistors disabled.
4. Examples calculated using V
IL
relation, V
DD
, and max I
IND
: Z
IND
=V
IL
/I
IND
. This is the impedance needed to pull a high
signal to a level below V
IL
due to leakage when V
IL
< V
IN
< V
DD
. These examples assume signal source low = 0 V. See
Figure 1.
5. Measured at V
DD
supply voltage = V
DD
min and Vinput = V
SS
6. Measured at V
DD
supply voltage = V
DD
min and Vinput = V
DD
Figure 2. 5 V Tolerant Input IIND Parameter
5.2.4 Power mode transition operating behaviors
All specifications except t
POR
, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 150 MHz
• Bus clock = 75 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode: FEI
Table 5. Power mode transition operating behaviors
Symbol Description Min. Max. Unit Notes
t
POR
After a POR event, amount of time from the point V
DD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• V
DD
slew rate ≥ 5.7 kV/s
• V
DD
slew rate < 5.7 kV/s
—
—
300
1.7 V / (V
DD
slew rate)
μs
1
• VLLS1 → RUN
— 160 μs
• VLLS2 → RUN
— 114 μs
• VLLS3 → RUN
— 114 μs
Table continues on the next page...
General
K60 Sub-Family, Rev5, 10/2013.
16 Freescale Semiconductor, Inc.