Datasheet

2. V
DD_INT
3. V
DDA
4. V
DD_DDR
The power-down sequence is the reverse:
1. V
DD_DDR
2. V
DDA
3. V
DD_INT
4. V
DD
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol Description Min. Max. Unit
T
cyc
Clock period Frequency dependent MHz
T
wl
Low pulse width 2 — ns
T
wh
High pulse width 2 — ns
T
r
Clock and data rise time — 3 ns
T
f
Clock and data fall time — 3 ns
T
s
Data setup 3 — ns
T
h
Data hold 2 — ns
Figure 5. TRACE_CLKOUT specifications
Peripheral operating requirements and behaviors
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc. 25