Datasheet
J7
J8
J7
J5
J6
Input data valid
Output data valid
Output data valid
TCLK
Data inputs
Data outputs
Data outputs
Data outputs
Figure 8. Boundary scan (JTAG) timing
J11
J12
J11
J9
J10
Input data valid
Output data valid
Output data valid
TCLK
TDI/TMS
TDO
TDO
TDO
Figure 9. Test Access Port timing
Peripheral operating requirements and behaviors
K60 Sub-Family, Rev5, 10/2013.
28 Freescale Semiconductor, Inc.
