Datasheet

Table 15. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
f
dco
DCO output
frequency range
Low range (DRS=00)
640 × f
fll_ref
20 20.97 25 MHz 2, 3
Mid range (DRS=01)
1280 × f
fll_ref
40 41.94 50 MHz
Mid-high range (DRS=10)
1920 × f
fll_ref
60 62.91 75 MHz
High range (DRS=11)
2560 × f
fll_ref
80 83.89 100 MHz
f
dco_t_DMX32
DCO output
frequency
Low range (DRS=00)
732 × f
fll_ref
— 23.99 — MHz 4
Mid range (DRS=01)
1464 × f
fll_ref
— 47.97 — MHz
Mid-high range (DRS=10)
2197 × f
fll_ref
— 71.99 — MHz
High range (DRS=11)
2929 × f
fll_ref
— 95.98 — MHz
J
cyc_fll
FLL period jitter
• f
VCO
= 48 MHz
• f
VCO
= 98 MHz
—
—
180
150
—
—
ps
t
fll_acquire
FLL target frequency acquisition time — — 1 ms 6
PLL0,1
f
pll_ref
PLL reference frequency range 8 — 16 MHz
f
vcoclk_2x
VCO output frequency
180
—
360
MHz
f
vcoclk
PLL output frequency
90
—
180
MHz
f
vcoclk_90
PLL quadrature output frequency
90
—
180
MHz
I
pll
PLL0 operating current
• VCO @ 180 MHz (f
osc_hi_1
= 32 MHz, f
pll_ref
= 8 MHz, VDIV multiplier = 22)
— 2.8 — mA
I
pll
PLL0 operating current
• VCO @ 360 MHz (f
osc_hi_1
= 32 MHz, f
pll_ref
= 8 MHz, VDIV multiplier = 45)
— 4.7 — mA
6
I
pll
PLL1 operating current
• VCO @ 180 MHz (f
osc_hi_1
= 32 MHz, f
pll_ref
= 8 MHz, VDIV multiplier = 22)
— 2.3 — mA
6
I
pll
PLL1 operating current
• VCO @ 360 MHz (f
osc_hi_1
= 32 MHz, f
pll_ref
= 8 MHz, VDIV multiplier = 45)
— 3.6 — mA
6
t
pll_lock
Lock detector detection time — — 100 × 10
-6
+ 1075(1/
f
pll_ref
)
s
J
cyc_pll
PLL period jitter (RMS)
Table continues on the next page...
Peripheral operating requirements and behaviors
K60 Sub-Family, Rev5, 10/2013.
30 Freescale Semiconductor, Inc.