Datasheet

Table 24. EzPort switching specifications (continued)
Num Description Min. Max. Unit
EP4 EZP_CK high to EZP_CS input invalid (hold) 5 — ns
EP5 EZP_D input valid to EZP_CK high (setup) 2 — ns
EP6 EZP_CK high to EZP_D input invalid (hold) 5 — ns
EP7 EZP_CK low to EZP_Q output valid — 16 ns
EP8 EZP_CK low to EZP_Q output invalid (hold) 0 — ns
EP9 EZP_CS negation to EZP_Q tri-state — 12 ns
EP2
EP3
EP4
EP5 EP6
EP7
EP8
EP9
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Figure 12. EzPort Timing Diagram
6.4.3 NFC specifications
The NAND flash controller (NFC) implements the interface to standard NAND flash
memory devices. This section describes the timing parameters of the NFC.
In the following table:
• T
H
is the flash clock high time and
• T
L
is flash clock low time,
which are defined as:
input clock
T
SCALER
=
NFC
T
=
H
T
L
T
+
Peripheral operating requirements and behaviors
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc. 39