Datasheet

tCS tCH
tWP
tDS tDH
data
data
data
tWC
tWH
NFC_CEn
NFC_WE
NFC_IOn
Figure 15. Write data latch cycle timing
tCH
tRP
data
data
data
tRC
tREH
tIS
tRR
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
Figure 16. Read data latch cycle timing in non-fast mode
tCH
tRP
data
data
data
tRC
tREH
tIS
tRR
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
Figure 17. Read data latch cycle timing in fast mode
6.4.4 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
Peripheral operating requirements and behaviors
K60 Sub-Family, Rev5, 10/2013.
42 Freescale Semiconductor, Inc.