Datasheet

Figure 22. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
6.6.1.3 16-bit ADC with PGA operating conditions
Table 30. 16-bit ADC with PGA operating conditions
Symbol Description Conditions Min. Typ.
1
Max. Unit Notes
V
DDA
Supply voltage Absolute 1.71 — 3.6 V
V
REFPGA
PGA ref voltage VREF_OU
T
VREF_OU
T
VREF_OU
T
V 2, 3
V
ADIN
Input voltage V
SSA
— V
DDA
V
V
CM
Input Common
Mode range
V
SSA
— V
DDA
V
R
PGAD
Differential input
impedance
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
—
—
—
128
64
32
—
—
—
kΩ IN+ to IN-
4
R
AS
Analog source
resistance
— 100 — Ω 5
T
S
ADC sampling
time
1.25 — — µs 6
C
rate
ADC conversion
rate
≤ 13 bit modes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
18.484 — 450 Ksps 7
Table continues on the next page...
Peripheral operating requirements and behaviors
K60 Sub-Family, Rev5, 10/2013.
50 Freescale Semiconductor, Inc.