Datasheet
Table 31. 16-bit ADC with PGA characteristics (continued)
Symbol Description Conditions Min. Typ.
1
Max. Unit Notes
• Gain=64, Average=8
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
6.3
12.8
11.0
7.9
7.3
6.8
6.8
7.5
9.6
14.5
14.3
13.8
13.1
12.5
11.5
10.6
—
—
—
—
—
—
—
—
bits
bits
bits
bits
bits
bits
bits
bits
SINAD Signal-to-noise
plus distortion
ratio
See ENOB 6.02 × ENOB + 1.76 dB
1. Typical values assume V
DDA
=3.0V, Temp=25°C, f
ADCK
=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (V
CM
) and the PGA gain.
4. Gain = 2
PGAG
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 32. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
V
DD
Supply voltage 1.71 — 3.6 V
I
DDHS
Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA
I
DDLS
Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA
V
AIN
Analog input voltage V
SS
– 0.3 — V
DD
V
V
AIO
Analog input offset voltage — — 20 mV
V
H
Analog comparator hysteresis
1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
10
20
30
—
—
—
—
mV
mV
mV
mV
V
CMPOh
Output high V
DD
– 0.5 — — V
V
CMPOl
Output low — — 0.5 V
t
DHS
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20 50 200 ns
t
DLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
80 250 600 ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc. 53