Datasheet

Table 32. Comparator and 6-bit DAC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit
Analog comparator initialization delay
2
— — 40 μs
I
DAC6b
6-bit DAC current adder (enabled) — 7 — μA
INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB
3
DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to V
DD
–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = V
reference
/64
0.04
0.05
0.06
0.07
0.08
P Hystereris (V)
00
01
10
HYSTCTR
Setting
0
0.01
0.02
0.03
0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1
CM
10
11
Vin level (V)
Figure 23. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Peripheral operating requirements and behaviors
K60 Sub-Family, Rev5, 10/2013.
54 Freescale Semiconductor, Inc.