Datasheet

Table 50. SDHC switching specifications over the full operating voltage
range
Num Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
Card input clock
SD1 fpp Clock frequency (low speed) 0 400 kHz
fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz
fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz
f
OD
Clock frequency (identification mode) 0 400 kHz
SD2 t
WL
Clock low time 7 — ns
SD3 t
WH
Clock high time 7 — ns
SD4 t
TLH
Clock rise time — 3 ns
SD5 t
THL
Clock fall time — 3 ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6 t
OD
SDHC output delay (output valid) -5 6.5 ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7 t
ISU
SDHC input setup time 5 — ns
SD8 t
IH
SDHC input hold time 1.3 — ns
SD2SD3 SD1
SD6
SD8
SD7
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 35. SDHC timing
6.8.12 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
Peripheral operating requirements and behaviors
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc. 69