Datasheet

S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 36. I2S/SAI timing — master modes
Table 52. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(limited voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 2.7 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
• Multiple SAI Synchronous mode
• All other modes
—
—
21
15
ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns
S17 I2S_RXD setup before I2S_RX_BCLK 4.5 — ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid
1
— 25 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Peripheral operating requirements and behaviors
K60 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc. 71