Datasheet

S15

S13

S15

S17 S18

S15

S16

S14

S16

S11

S12

I2S_TX_BCLK/

I2S_RX_BCLK (input)

I2S_TX_FS/

I2S_RX_FS (output)

I2S_TXD

I2S_RXD

I2S_TX_FS/

I2S_RX_FS (input)

S19

Figure 39. I2S/SAI timing — slave modes

6.8.12.3 VLPR, VLPW, and VLPS mode performance over the full

operating voltage range

This section provides the operating performance over the full operating voltage for the

device in VLPR, VLPW, and VLPS modes.

Table 55. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes

(full voltage range)

Num. Characteristic Min. Max. Unit

Operating voltage 1.71 3.6 V

S1 I2S_MCLK cycle time 62.5 — ns

S2 I2S_MCLK pulse width high/low 45% 55% MCLK period

S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 — ns

S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period

S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output valid

— 45 ns

S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output invalid

0 — ns

S7 I2S_TX_BCLK to I2S_TXD valid — 45 ns

S8 I2S_TX_BCLK to I2S_TXD invalid -1.6 — ns

S9 I2S_RXD/I2S_RX_FS input setup before

I2S_RX_BCLK

45 — ns

S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns

Peripheral operating requirements and behaviors

K60 Sub-Family, Rev5, 10/2013.

74 Freescale Semiconductor, Inc.