Datasheet

Table 58. Pins with active pull control after reset
Pin Active pull direction after reset
PTA0 pulldown
PTA1 pullup
PTA3 pullup
PTA4 pullup
RESET_b pullup
8.2 K60 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
144
LQFP
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
— L5 RTC_
WAKEUP_B
RTC_
WAKEUP_B
RTC_
WAKEUP_B
— M5 NC NC NC
— A10 NC NC NC
— B10 NC NC NC
— C10 NC NC NC
1 D3 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA RTC_CLKOUT
2 D2 PTE1/
LLWU_P0
ADC1_SE5a ADC1_SE5a PTE1/
LLWU_P0
SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL SPI1_SIN
3 D1 PTE2/
LLWU_P1
ADC1_SE6a ADC1_SE6a PTE2/
LLWU_P1
SPI1_SCK UART1_CTS_
b
SDHC0_DCLK
4 E4 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_
b
SDHC0_CMD SPI1_SOUT
5 E5 VDD VDD VDD
6 F6 VSS VSS VSS
7 E3 PTE4/
LLWU_P2
DISABLED PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX SDHC0_D3
8 E2 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 FTM3_CH0
9 E1 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_
b
I2S0_MCLK FTM3_CH1 USB_SOF_
OUT
10 F4 PTE7 DISABLED PTE7 UART3_RTS_
b
I2S0_RXD0 FTM3_CH2
11 F3 PTE8 ADC2_SE16 ADC2_SE16 PTE8 I2S0_RXD1 UART5_TX I2S0_RX_FS FTM3_CH3
12 F2 PTE9 ADC2_SE17 ADC2_SE17 PTE9 I2S0_TXD1 UART5_RX I2S0_RX_
BCLK
FTM3_CH4
13 F1 PTE10 DISABLED PTE10 UART5_CTS_
b
I2S0_TXD0 FTM3_CH5
Pinout
K60 Sub-Family, Rev5, 10/2013.
78 Freescale Semiconductor, Inc.