Datasheet

144
LQFP
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
132 A3 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_
b/
UART0_COL_
b
FTM0_CH5 FB_AD1/
NFC_DATA0
EWM_OUT_b
133 A2 PTD6/
LLWU_P15
ADC0_SE7b ADC0_SE7b PTD6/
LLWU_P15
SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0
134 M10 VSS VSS VSS
135 F8 VDD VDD VDD
136 A1 PTD7 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1
137 C9 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16/
NFC_CLE
138 B9 PTD9 DISABLED PTD9 I2C0_SDA UART5_TX FB_A17/
NFC_ALE
139 B3 PTD10 DISABLED PTD10 UART5_RTS_
b
FB_A18/
NFC_RE
140 B2 PTD11 DISABLED PTD11 SPI2_PCS0 UART5_CTS_
b
SDHC0_
CLKIN
FB_A19
141 B1 PTD12 DISABLED PTD12 SPI2_SCK FTM3_FLT0 SDHC0_D4 FB_A20
142 C3 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21
143 C2 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22
144 C1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23
8.3 K61 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
D3 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA RTC_CLKOUT
D2 PTE1/
LLWU_P0
ADC1_SE5a ADC1_SE5a PTE1/
LLWU_P0
SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL SPI1_SIN
D1 PTE2/
LLWU_P1
ADC1_SE6a ADC1_SE6a PTE2/
LLWU_P1
SPI1_SCK UART1_CTS_b SDHC0_DCLK
E4 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_b SDHC0_CMD SPI1_SOUT
E5 VDD VDD VDD
F6 VSS VSS VSS
E3 PTE4/
LLWU_P2
DISABLED PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX SDHC0_D3
E2 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 FTM3_CH0
E1 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_b I2S0_MCLK FTM3_CH1 USB_SOF_
OUT
Pinout
K60 Sub-Family, Rev5, 10/2013.
84 Freescale Semiconductor, Inc.