Datasheet

1 2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
G
H
J
10
K
K
10
11
11
LL
12
12
M
M
PTA18
PTC8
LLWU_P8
NC
LLWU_P7
PTC2
PTA1 PTA6PTA0PTE27
ADC0_SE16/
ADC1_SE16/
PTE26 PTE25 PTA2 PTA3 PTA8
PTA7
VSSVSSVSSAVDDAPTE28VSSUSB0_DM
PGA2_DM/
PGA3_DM/
PGA0_DM/ DAC0_OUT/
DAC1_OUT/
WAKEUP_B
VBAT
LLWU_P3
PTA9 PTA11
PTA12
LLWU_P4
PTB1
PTA27
LLWU_P5
PTB4PTB5VSSVSSVREFLVREFHPTE11PTE12VREGINVOUT33
USB0_DP
PGA2_DP/
PGA3_DP/
PGA0_DP/
PGA1_DP/ PGA1_DM/
VREF_OUT/
PTE24 NC EXTAL32 XTAL32 PTA5 PTA10 VSS
PTA16
PTA14
PTB3
PTA29
PTA26
PTA17
PTA15
PTA19
RESET_b
PTA24
PTA25
PTA28
PTB2
PTB6PTB7PTB8PTB9VDD
VDD PTB17 PTB16 PTB10PTB11
PTB19 PTB18
PTB22PTB23NC
PTB20PTB21
LLWU_P9
PTD8
LLWU_P10
PTC7 PTD9 NC
LLWU_P6
PTC0
VSS VSS
VDDVDD
PTC13 PTC9
LLWU_P11
PTC10
PTC19 PTC15
PTC14PTC18
LLWU_P13
PTD3PTD10
PTD13
PTE0 PTD1 PTC17
VDD
VDDPTE7
PTE3
LLWU_P2
PTE8PTE9PTE10
PTE6 PTE5
LLWU_P0LLWU_P1
PTD15 PTD14
PTD11PTD12
PTC12PTC16
LLWU_P12LLWU_P14
PTD5
LLWU_P15
PTD7
ADC1_DP0/
ADC0_DP3
ADC1_DM0/
ADC0_DM3
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
PTA4/
ADC0_DP0/
ADC1_DP3
ADC0_DM0/
ADC1_DM3
CMP1_IN3/
ADC0_SE23
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
RTC_
ADC2_DP3/
ADC1_DP1
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
CMP2_IN2/
ADC0_SE22
PTA13/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
CMP1_IN2/
ADC0_SE21
PTB0/
PTE4/
PTE2/ PTE1/ PTC5/
PTC6/PTD2/
PTC11/ PTC1/
PTC3/PTC4/
PTD0/PTD4/PTD6/
Figure 43. K60 144 MAPBGA Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
Table 59. Revision History
Rev. No. Date Substantial Changes
3 3/2012 Initial public release
Table continues on the next page...
Revision History
K60 Sub-Family, Rev5, 10/2013.
92 Freescale Semiconductor, Inc.